[PATCH] D141966: [RISCV] Eliminate the need to pass both RISCVSubtarget and MCSubtargetInfo to isCompressibleInst.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jan 17 18:28:52 PST 2023


This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa971ce70aa04: [RISCV] Eliminate the need to pass both RISCVSubtarget and MCSubtargetInfo to… (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141966/new/

https://reviews.llvm.org/D141966

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/utils/TableGen/CompressInstEmitter.cpp


Index: llvm/utils/TableGen/CompressInstEmitter.cpp
===================================================================
--- llvm/utils/TableGen/CompressInstEmitter.cpp
+++ llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -54,8 +54,7 @@
 // an instruction is compressable:
 //
 // bool isCompressibleInst(const MachineInstr& MI,
-//                         const <TargetName>Subtarget *Subtarget,
-//                         const MCSubtargetInfo &STI);
+//                         const <TargetName>Subtarget &STI);
 //
 // The clients that include this auto-generated header file and
 // invoke these functions can compress an instruction before emitting
@@ -613,8 +612,7 @@
     FuncH.indent(27) << "const MCSubtargetInfo &STI) {\n";
   } else if (EType == EmitterType::CheckCompress) {
     FuncH << "static bool isCompressibleInst(const MachineInstr &MI,\n";
-    FuncH.indent(31) << "const " << TargetName << "Subtarget *Subtarget,\n";
-    FuncH.indent(31) << "const MCSubtargetInfo &STI) {\n";
+    FuncH.indent(31) << "const " << TargetName << "Subtarget &STI) {\n";
   }
 
   if (CompressPatterns.empty()) {
@@ -786,7 +784,7 @@
                 << "MI.getOperand(" << OpIdx << ").isImm() &&\n";
             CondStream.indent(6) << TargetName << "ValidateMachineOperand("
                                  << "MI.getOperand(" << OpIdx
-                                 << "), Subtarget, " << Entry << ") &&\n";
+                                 << "), &STI, " << Entry << ") &&\n";
           }
           if (CompressOrUncompress)
             CodeStream.indent(6)
@@ -808,7 +806,7 @@
           CondStream.indent(6)
               << TargetName
               << "ValidateMachineOperand(MachineOperand::CreateImm("
-              << DestOperandMap[OpNo].Data.Imm << "), SubTarget, " << Entry
+              << DestOperandMap[OpNo].Data.Imm << "), &STI, " << Entry
               << ") &&\n";
         }
         if (CompressOrUncompress)
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1205,11 +1205,7 @@
   }
 
   if (MI.getParent() && MI.getParent()->getParent()) {
-    const auto MF = MI.getMF();
-    const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget());
-    const MCSubtargetInfo &STI = *TM.getMCSubtargetInfo();
-    const RISCVSubtarget &ST = MF->getSubtarget<RISCVSubtarget>();
-    if (isCompressibleInst(MI, &ST, STI))
+    if (isCompressibleInst(MI, STI))
       return 2;
   }
   return get(Opcode).getSize();


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