[PATCH] D141951: [RISCV] Remove MCRegisterInfo dependency from uncompresInst and isCompressibleInst.

[Craig Topper via Phabricator via llvm-commits]

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This was being used to lookup the register class for a register number,
but those live in a tablegened array. We can index that array directly
just like RISCVAsmParser does.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141951

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/test/TableGen/AsmPredicateCombiningRISCV.td
  llvm/utils/TableGen/CompressInstEmitter.cpp

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