[PATCH] D141937: [SVE] Add intrinsics for integer binops that explicitly undefine the result for inactive lanes.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added reviewers: sdesmalen, kmclaughlin, david-arm.
paulwalker-arm added a comment.

This along with D141939 <https://reviews.llvm.org/D141939> forms my counter proposal to D141240 <https://reviews.llvm.org/D141240> and represents my preferred option.  The only downside that I can see is that some existing instruction combines might need to be updated to also consider these new intrinsics.  With that said the combines we typically do are likely not necessary for these intrinsics because we can now do similar transformation during code generation (for example converting add+mul to mla) with those transformations likely to be desirable for auto-vectorised IR anyway. D141938 <https://reviews.llvm.org/D141938> shows the more immediate benefit of these intrinsics in freeing up isel to allow better code generation.

NOTE: If this proves the winning design then I'm tempted to add instruction simplications to convert calls to the existing intrinsics where the predicate is all active to these new _u forms.  Doing this will allow us to remove some duplication when pattern matching and also mean function like `convertMergedOpToPredOp` become redundant.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D141937/new/

https://reviews.llvm.org/D141937