[PATCH] D141289: [MIScheduler] Print top/down cycle in the SUnit dump.

[Francesco Petrogalli via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG229162d4d744: [MIScheduler] Print top/down cycle in the SUnit dump. (authored by fpetrogalli).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141289/new/

https://reviews.llvm.org/D141289

Files:
  llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
  llvm/test/CodeGen/AArch64/sched-print-cycle.mir


Index: llvm/test/CodeGen/AArch64/sched-print-cycle.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sched-print-cycle.mir
@@ -0,0 +1,29 @@
+# RUN: llc -mtriple=arm64-apple-macos -mcpu=apple-m1 -sched-print-cycles=true \
+# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s
+
+# RUN: llc -mtriple=arm64-apple-macos -mcpu=apple-m1 -sched-print-cycles=false \
+# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s --check-prefix=NOCYCLES
+
+# REQUIRES: asserts
+---
+name: mul_mul
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x0
+    $x1 = ADDXrr $x0, $x0
+    $x2 = ADDXrr $x1, $x1
+    $x3 = ADDXrr $x2, $x2
+    $x4 = ADDXrr $x2, $x2
+
+# CHECK-LABEL: *** Final schedule for %bb.0 ***
+# CHECK-NEXT: SU(0) [TopReadyCycle = 0, BottomReadyCycle = 0]:   $x1 = ADDXrr $x0, $x0
+# CHECK-NEXT: SU(1) [TopReadyCycle = 0, BottomReadyCycle = 1]:   $x2 = ADDXrr $x1, $x1
+# CHECK-NEXT: SU(2) [TopReadyCycle = 1, BottomReadyCycle = 0]:   $x3 = ADDXrr $x2, $x2
+# CHECK-NEXT: SU(3) [TopReadyCycle = 1, BottomReadyCycle = 0]:   $x4 = ADDXrr $x2, $x2
+
+# NOCYCLES-LABEL: *** Final schedule for %bb.0 ***
+# NOCYCLES-NEXT: SU(0):   $x1 = ADDXrr $x0, $x0
+# NOCYCLES-NEXT: SU(1):   $x2 = ADDXrr $x1, $x1
+# NOCYCLES-NEXT: SU(2):   $x3 = ADDXrr $x2, $x2
+# NOCYCLES-NEXT: SU(3):   $x4 = ADDXrr $x2, $x2
Index: llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
===================================================================
--- llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -84,6 +84,12 @@
     cl::desc("A huge scheduling region will have maps reduced by this many "
              "nodes at a time. Defaults to HugeRegion / 2."));
 
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
+static cl::opt<bool> SchedPrintCycles(
+    "sched-print-cycles", cl::Hidden, cl::init(false),
+    cl::desc("Report top/bottom cycles when dumping SUnit instances"));
+#endif
+
 static unsigned getReductionSize() {
   // Always reduce a huge region with half of the elements, except
   // when user sets this number explicitly.
@@ -1158,6 +1164,9 @@
 void ScheduleDAGInstrs::dumpNode(const SUnit &SU) const {
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
   dumpNodeName(SU);
+  if (SchedPrintCycles)
+    dbgs() << " [TopReadyCycle = " << SU.TopReadyCycle
+           << ", BottomReadyCycle = " << SU.BotReadyCycle << "]";
   dbgs() << ": ";
   SU.getInstr()->dump();
 #endif


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