[llvm] 229162d - [MIScheduler] Print top/down cycle in the SUnit dump.

[Francesco Petrogalli via llvm-commits]

Author: Francesco Petrogalli
Date: 2023-01-17T15:55:43+01:00
New Revision: 229162d4d7440da09507b5dfc6f72178effdcc6c

URL: https://github.com/llvm/llvm-project/commit/229162d4d7440da09507b5dfc6f72178effdcc6c
DIFF: https://github.com/llvm/llvm-project/commit/229162d4d7440da09507b5dfc6f72178effdcc6c.diff

LOG: [MIScheduler] Print top/down cycle in the SUnit dump.

Add an extra command line option to `llc` that allows checking at what cycle an instruction has been scheduled by the machine scheduler.

Differential Revision: https://reviews.llvm.org/D141289

Added: 
    llvm/test/CodeGen/AArch64/sched-print-cycle.mir

Modified: 
    llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index 06ffd6376ac2f..1b213e87e75cf 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -84,6 +84,12 @@ static cl::opt<unsigned> ReductionSize(
     cl::desc("A huge scheduling region will have maps reduced by this many "
              "nodes at a time. Defaults to HugeRegion / 2."));
 
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
+static cl::opt<bool> SchedPrintCycles(
+    "sched-print-cycles", cl::Hidden, cl::init(false),
+    cl::desc("Report top/bottom cycles when dumping SUnit instances"));
+#endif
+
 static unsigned getReductionSize() {
   // Always reduce a huge region with half of the elements, except
   // when user sets this number explicitly.
@@ -1158,6 +1164,9 @@ void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) {
 void ScheduleDAGInstrs::dumpNode(const SUnit &SU) const {
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
   dumpNodeName(SU);
+  if (SchedPrintCycles)
+    dbgs() << " [TopReadyCycle = " << SU.TopReadyCycle
+           << ", BottomReadyCycle = " << SU.BotReadyCycle << "]";
   dbgs() << ": ";
   SU.getInstr()->dump();
 #endif

diff  --git a/llvm/test/CodeGen/AArch64/sched-print-cycle.mir b/llvm/test/CodeGen/AArch64/sched-print-cycle.mir
new file mode 100644
index 0000000000000..59c51571df74b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sched-print-cycle.mir
@@ -0,0 +1,29 @@
+# RUN: llc -mtriple=arm64-apple-macos -mcpu=apple-m1 -sched-print-cycles=true \
+# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s
+
+# RUN: llc -mtriple=arm64-apple-macos -mcpu=apple-m1 -sched-print-cycles=false \
+# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s --check-prefix=NOCYCLES
+
+# REQUIRES: asserts
+---
+name: mul_mul
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x0
+    $x1 = ADDXrr $x0, $x0
+    $x2 = ADDXrr $x1, $x1
+    $x3 = ADDXrr $x2, $x2
+    $x4 = ADDXrr $x2, $x2
+
+# CHECK-LABEL: *** Final schedule for %bb.0 ***
+# CHECK-NEXT: SU(0) [TopReadyCycle = 0, BottomReadyCycle = 0]:   $x1 = ADDXrr $x0, $x0
+# CHECK-NEXT: SU(1) [TopReadyCycle = 0, BottomReadyCycle = 1]:   $x2 = ADDXrr $x1, $x1
+# CHECK-NEXT: SU(2) [TopReadyCycle = 1, BottomReadyCycle = 0]:   $x3 = ADDXrr $x2, $x2
+# CHECK-NEXT: SU(3) [TopReadyCycle = 1, BottomReadyCycle = 0]:   $x4 = ADDXrr $x2, $x2
+
+# NOCYCLES-LABEL: *** Final schedule for %bb.0 ***
+# NOCYCLES-NEXT: SU(0):   $x1 = ADDXrr $x0, $x0
+# NOCYCLES-NEXT: SU(1):   $x2 = ADDXrr $x1, $x1
+# NOCYCLES-NEXT: SU(2):   $x3 = ADDXrr $x2, $x2
+# NOCYCLES-NEXT: SU(3):   $x4 = ADDXrr $x2, $x2