[PATCH] D141214: [InstCombine] Don't combine smul of i1 type constant one

[luxufan via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0ad590995815: [InstCombine] Don't combine smul of i1 type constant one (authored by StephenFan).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141214/new/

https://reviews.llvm.org/D141214

Files:
  llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
  llvm/test/Transforms/InstCombine/smulo.ll


Index: llvm/test/Transforms/InstCombine/smulo.ll
===================================================================
--- llvm/test/Transforms/InstCombine/smulo.ll
+++ llvm/test/Transforms/InstCombine/smulo.ll
@@ -160,7 +160,7 @@
 
 define i1 @i1_ov_by_one(i1 %x) {
 ; CHECK-LABEL: @i1_ov_by_one(
-; CHECK-NEXT:    ret i1 false
+; CHECK-NEXT:    ret i1 [[X:%.*]]
 ;
   %m = call {i1, i1} @llvm.smul.with.overflow.i1(i1 %x, i1 1)
   %ov = extractvalue {i1, i1} %m, 1
@@ -169,7 +169,7 @@
 
 define <2 x i1> @v2i1_ov_by_one(<2 x i1> %x) {
 ; CHECK-LABEL: @v2i1_ov_by_one(
-; CHECK-NEXT:    ret <2 x i1> zeroinitializer
+; CHECK-NEXT:    ret <2 x i1> [[X:%.*]]
 ;
   %m = call {<2 x i1>, <2 x i1>} @llvm.smul.with.overflow.v2i1(<2 x i1> %x, <2 x i1> <i1 1, i1 1>)
   %ov = extractvalue {<2 x i1>, <2 x i1>} %m, 1
Index: llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
===================================================================
--- llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -4986,7 +4986,7 @@
   return foldICmpWithZextOrSext(ICmp);
 }
 
-static bool isNeutralValue(Instruction::BinaryOps BinaryOp, Value *RHS) {
+static bool isNeutralValue(Instruction::BinaryOps BinaryOp, Value *RHS, bool IsSigned) {
   switch (BinaryOp) {
     default:
       llvm_unreachable("Unsupported binary op");
@@ -4994,7 +4994,8 @@
     case Instruction::Sub:
       return match(RHS, m_Zero());
     case Instruction::Mul:
-      return match(RHS, m_One());
+      return !(RHS->getType()->isIntOrIntVectorTy(1) && IsSigned) &&
+             match(RHS, m_One());
   }
 }
 
@@ -5041,7 +5042,7 @@
   if (auto *LHSTy = dyn_cast<VectorType>(LHS->getType()))
     OverflowTy = VectorType::get(OverflowTy, LHSTy->getElementCount());
 
-  if (isNeutralValue(BinaryOp, RHS)) {
+  if (isNeutralValue(BinaryOp, RHS, IsSigned)) {
     Result = LHS;
     Overflow = ConstantInt::getFalse(OverflowTy);
     return true;


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