[llvm] 78ba3e7 - [AArch64][SVE] Fix typo after post review change to D141471.

[Paul Walker via llvm-commits]

Author: Paul Walker
Date: 2023-01-17T13:08:43Z
New Revision: 78ba3e785cda23aa3bdf015988925e7f340f077a

URL: https://github.com/llvm/llvm-project/commit/78ba3e785cda23aa3bdf015988925e7f340f077a
DIFF: https://github.com/llvm/llvm-project/commit/78ba3e785cda23aa3bdf015988925e7f340f077a.diff

LOG: [AArch64][SVE] Fix typo after post review change to D141471.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index eeaa8edb7cc5..3370da479e3c 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -558,8 +558,8 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
   if (FalseZero) {
     // If we cannot prefix the requested instruction we'll instead emit a
     // prefixed_zeroing_mov for DestructiveBinary.
-    assert((DOPRegIsUnique || ((DType == AArch64::DestructiveBinary) ||
-                               (DType = AArch64::DestructiveBinaryComm))) &&
+    assert((DOPRegIsUnique || DType == AArch64::DestructiveBinary ||
+            DType == AArch64::DestructiveBinaryComm) &&
            "The destructive operand should be unique");
     assert(ElementSize != AArch64::ElementSizeNone &&
            "This instruction is unpredicated");
@@ -576,8 +576,8 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
     // Create the additional LSL to zero the lanes when the DstReg is not
     // unique. Zeros the lanes in z0 that aren't active in p0 with sequence
     // movprfx z0.b, p0/z, z0.b; lsl z0.b, p0/m, z0.b, #0;
-    if (((DType == AArch64::DestructiveBinary) ||
-         (DType == AArch64::DestructiveBinaryComm)) &&
+    if ((DType == AArch64::DestructiveBinary ||
+         DType == AArch64::DestructiveBinaryComm) &&
         !DOPRegIsUnique) {
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LSLZero))
           .addReg(DstReg, RegState::Define)