[PATCH] D141806: [X86] `canonicalizeShuffleWithBinOps()`: support `VS[HR][LA]I` opcodes (unary shuffles only)

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri updated this revision to Diff 489640.
lebedev.ri marked an inline comment as done.
lebedev.ri edited the summary of this revision.
lebedev.ri added a comment.

@RKSimon thank you for taking a look!
Indeed, that does solve my concerns.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141806/new/

https://reviews.llvm.org/D141806

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/abds-vector-128.ll
  llvm/test/CodeGen/X86/abdu-vector-128.ll
  llvm/test/CodeGen/X86/avx512-cmp.ll
  llvm/test/CodeGen/X86/blend-of-shift.ll
  llvm/test/CodeGen/X86/combine-abs.ll
  llvm/test/CodeGen/X86/combine-mul.ll
  llvm/test/CodeGen/X86/combine-sdiv.ll
  llvm/test/CodeGen/X86/freeze-binary.ll
  llvm/test/CodeGen/X86/known-signbits-vector.ll
  llvm/test/CodeGen/X86/packss.ll
  llvm/test/CodeGen/X86/pr32907.ll
  llvm/test/CodeGen/X86/promote-cmp.ll
  llvm/test/CodeGen/X86/rotate_vec.ll
  llvm/test/CodeGen/X86/sadd_sat_vec.ll
  llvm/test/CodeGen/X86/sdiv_fix_sat.ll
  llvm/test/CodeGen/X86/select-sra.ll
  llvm/test/CodeGen/X86/shift-logic.ll
  llvm/test/CodeGen/X86/shrink_vmul.ll
  llvm/test/CodeGen/X86/shuffle-of-shift.ll
  llvm/test/CodeGen/X86/ssub_sat_vec.ll
  llvm/test/CodeGen/X86/vector-sext.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
  llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
  llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll
  llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll
  llvm/test/CodeGen/X86/viabs.ll
  llvm/test/CodeGen/X86/vselect-zero.ll
  llvm/test/CodeGen/X86/vselect.ll
  llvm/test/CodeGen/X86/vshift-3.ll
  llvm/test/CodeGen/X86/vsplit-and.ll

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