[PATCH] D141728: [AMDGPU] Tune scheduler on GFX10 and GFX11

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D141728#4055501 <https://reviews.llvm.org/D141728#4055501>, @kerbowa wrote:

> 



> This situation is basically why the HighRPReschedule stage exists - where we target a higher occupancy to see if occupancy was dropped because the heuristics are not focusing RP reduction soon enough. This HighRP stage will only increase the target occupancy by one and decrease the critical register limit by an additional 10. We could probably be more aggressive with these numbers in cases where we have spilling. For example, setting the HighRPErrorMargin to something very high like 200 also eliminates the spilling in the testcase for the relevant ticket (SWDEV-377300).

In fact ErrorMargin is completely misused by the HighRPReschedule. This number is to account for the RPTracker inaccuracy, not to bias the limits. In this case it certainly does not help to bias SGPR limit by something like 200. I.e. it is possible to do it in the HighRPReschedule but it needs some better infrastructure.

The other consideration is that doing so only in the regions with high RP may leave little room for improvement. In the testcase discussed there is high enough livein pressure and it will not be affected as it comes from a block with a lesser pressure. On the other hand doing this math always makes it more balanced.


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