[PATCH] D141653: [X86] Improve instruction ordering of constant `srl/shl` with `and` to get better and-masks

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:47444
+combineLogicalShiftWithAnd(SDNode *N, SelectionDAG &DAG,
+                           TargetLowering::DAGCombinerInfo &DCI) {
+  // Only do this on the last DAG combine as it can interfere with other
----------------
a lot of the if-else complexity is coming from you trying to handle and(shift(x,c1),c2) and shift(and(x,c2),c3) permutations in the same code - can you not have 2 variants in separate wrapper functions and then have a simpler core function that both call?


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:47454
+  assert(N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SHL ||
+         N->getOpcode() == ISD::AND);
+
----------------
(style) assert message


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:47480
+  assert(ShiftOp->getOpcode() == ISD::SRL || ShiftOp->getOpcode() == ISD::SHL);
+  assert(AndOp->getOpcode() == ISD::AND);
+
----------------
(style) assert messages


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D141653/new/

https://reviews.llvm.org/D141653