[PATCH] D141469: [AArch64][SVE] Add more intrinsics in 'isZeroingInactiveLanes'.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:263-264
+  case ISD::VSELECT:
+    // Predicate select is slightly different, since there is only a full-vector
+    // predicate select (operating on svbool_t), so there are no inactive lanes.
+    if (Op.getValueType().getVectorElementType() == MVT::i1)
----------------
This comment only applies to the intrinsic, not to the ISD node.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:265-266
+    // predicate select (operating on svbool_t), so there are no inactive lanes.
+    if (Op.getValueType().getVectorElementType() == MVT::i1)
+      return true;
   case ISD::INTRINSIC_WO_CHAIN:
----------------
We can't make this generalisation to ISD::VSELECT because it doesn't necessarily zero the other lanes, e.g.

  define <vscale x 4 x i1> @foo(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %p0, <vscale x 4 x i1> %p1) {
    %1 = select <vscale x 4 x i1> %pg, <vscale x 4 x i1> %p0, <vscale x 4 x i1> %p1
    ret <vscale x 4 x i1> %1
  }
  
Is lowered to:
  
  foo:                                    // @foo
        sel     p0.b, p0, p1.b, p2.b
        ret

If p1.b and p2.b have non-zero values in their inactive lanes, then the result `p0.b` will also have non-zero values in the inactive lanes.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141469/new/

https://reviews.llvm.org/D141469