[PATCH] D141835: [WebAssembly][NFC] Add pre-commit test for D140069

[Luke Lau via Phabricator via llvm-commits]

luke created this revision.
luke added a reviewer: RKSimon.
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Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141835

Files:
  llvm/test/CodeGen/WebAssembly/simd-vectorized-load-splat.ll


Index: llvm/test/CodeGen/WebAssembly/simd-vectorized-load-splat.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/WebAssembly/simd-vectorized-load-splat.ll
@@ -0,0 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mattr=+simd128 | FileCheck %s
+
+; Ensures that vectorized loads that are really just splatted loads, are indeed
+; selected as splatted loads
+
+target triple = "wasm32-unknown-unknown"
+
+define <4 x i32> @load_splat_shuhffle_lhs(ptr %p) {
+; CHECK-LABEL: load_splat_shuhffle_lhs:
+; CHECK:         .functype load_splat_shuhffle_lhs (i32) -> (v128)
+; CHECK-NEXT:    .local v128
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    v128.load 0
+; CHECK-NEXT:    local.get 1
+; CHECK-NEXT:    i8x16.shuffle 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7
+; CHECK-NEXT:    # fallthrough-return
+  %a = load <2 x i64>, ptr %p
+  %b = shufflevector <2 x i64> %a, <2 x i64> poison, <2 x i32> <i32 0, i32 0>
+  %c = bitcast <2 x i64> %b to <4 x i32>
+  %d = shufflevector <4 x i32> %c, <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  ret <4 x i32> %d
+}
+
+define <4 x i32> @load_splat_shuffle_lhs_with_offset(ptr %p) {
+; CHECK-LABEL: load_splat_shuffle_lhs_with_offset:
+; CHECK:         .functype load_splat_shuffle_lhs_with_offset (i32) -> (v128)
+; CHECK-NEXT:    .local v128
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    v128.load 0
+; CHECK-NEXT:    local.get 1
+; CHECK-NEXT:    i8x16.shuffle 8, 9, 10, 11, 12, 13, 14, 15, 8, 9, 10, 11, 12, 13, 14, 15
+; CHECK-NEXT:    # fallthrough-return
+  %a = load <2 x i64>, ptr %p
+  %b = shufflevector <2 x i64> %a, <2 x i64> poison, <2 x i32> <i32 1, i32 undef>
+  %c = bitcast <2 x i64> %b to <4 x i32>
+  %d = shufflevector <4 x i32> %c, <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  ret <4 x i32> %d
+}
+
+define <4 x i32> @load_splat_shuffle_rhs(ptr %p) {
+; CHECK-LABEL: load_splat_shuffle_rhs:
+; CHECK:         .functype load_splat_shuffle_rhs (i32) -> (v128)
+; CHECK-NEXT:    .local v128
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    v128.load 0
+; CHECK-NEXT:    local.get 1
+; CHECK-NEXT:    i8x16.shuffle 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7
+; CHECK-NEXT:    # fallthrough-return
+  %a = load <2 x i64>, ptr %p
+  %b = shufflevector <2 x i64> poison, <2 x i64> %a, <2 x i32> <i32 2, i32 undef>
+  %c = bitcast <2 x i64> %b to <4 x i32>
+  %d = shufflevector <4 x i32> %c, <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  ret <4 x i32> %d
+}
+
+define <4 x i32> @load_splat_shuffle_rhs_with_offset(ptr %p) {
+; CHECK-LABEL: load_splat_shuffle_rhs_with_offset:
+; CHECK:         .functype load_splat_shuffle_rhs_with_offset (i32) -> (v128)
+; CHECK-NEXT:    .local v128
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    v128.load 0
+; CHECK-NEXT:    local.get 1
+; CHECK-NEXT:    i8x16.shuffle 8, 9, 10, 11, 12, 13, 14, 15, 8, 9, 10, 11, 12, 13, 14, 15
+; CHECK-NEXT:    # fallthrough-return
+  %a = load <2 x i64>, ptr %p
+  %b = shufflevector <2 x i64> poison, <2 x i64> %a, <2 x i32> <i32 3, i32 undef>
+  %c = bitcast <2 x i64> %b to <4 x i32>
+  %d = shufflevector <4 x i32> %c, <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  ret <4 x i32> %d
+}


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