[PATCH] D141834: [RISCV][NFC] Use uncompressInst to relax instructions
Wang Pengcheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 16 02:28:26 PST 2023
pcwang-thead created this revision.
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As the TODO said, we can just use generated uncompressInst to
relax instructions.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D141834
Files:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
@@ -14,6 +14,7 @@
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCFixupKindInfo.h"
+#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
namespace llvm {
@@ -23,16 +24,17 @@
class RISCVAsmBackend : public MCAsmBackend {
const MCSubtargetInfo &STI;
+ const MCRegisterInfo &MRI;
uint8_t OSABI;
bool Is64Bit;
bool ForceRelocs = false;
const MCTargetOptions &TargetOptions;
public:
- RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
- const MCTargetOptions &Options)
- : MCAsmBackend(support::little), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit),
- TargetOptions(Options) {
+ RISCVAsmBackend(const MCSubtargetInfo &STI, const MCRegisterInfo &MRI,
+ uint8_t OSABI, bool Is64Bit, const MCTargetOptions &Options)
+ : MCAsmBackend(support::little), STI(STI), MRI(MRI), OSABI(OSABI),
+ Is64Bit(Is64Bit), TargetOptions(Options) {
RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits());
}
~RISCVAsmBackend() override = default;
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -27,6 +27,10 @@
using namespace llvm;
+// Include the auto-generated portion of the compress emitter.
+#define GEN_UNCOMPRESS_INSTR
+#include "RISCVGenCompressInstEmitter.inc"
+
std::optional<MCFixupKind> RISCVAsmBackend::getFixupKind(StringRef Name) const {
if (STI.getTargetTriple().isOSBinFormatELF()) {
unsigned Type;
@@ -167,36 +171,15 @@
void RISCVAsmBackend::relaxInstruction(MCInst &Inst,
const MCSubtargetInfo &STI) const {
- // TODO: replace this with call to auto generated uncompressinstr() function.
MCInst Res;
switch (Inst.getOpcode()) {
default:
llvm_unreachable("Opcode not expected!");
case RISCV::C_BEQZ:
- // c.beqz $rs1, $imm -> beq $rs1, X0, $imm.
- Res.setOpcode(RISCV::BEQ);
- Res.addOperand(Inst.getOperand(0));
- Res.addOperand(MCOperand::createReg(RISCV::X0));
- Res.addOperand(Inst.getOperand(1));
- break;
case RISCV::C_BNEZ:
- // c.bnez $rs1, $imm -> bne $rs1, X0, $imm.
- Res.setOpcode(RISCV::BNE);
- Res.addOperand(Inst.getOperand(0));
- Res.addOperand(MCOperand::createReg(RISCV::X0));
- Res.addOperand(Inst.getOperand(1));
- break;
case RISCV::C_J:
- // c.j $imm -> jal X0, $imm.
- Res.setOpcode(RISCV::JAL);
- Res.addOperand(MCOperand::createReg(RISCV::X0));
- Res.addOperand(Inst.getOperand(0));
- break;
case RISCV::C_JAL:
- // c.jal $imm -> jal X1, $imm.
- Res.setOpcode(RISCV::JAL);
- Res.addOperand(MCOperand::createReg(RISCV::X1));
- Res.addOperand(Inst.getOperand(0));
+ uncompressInst(Res, Inst, MRI, STI);
break;
}
Inst = std::move(Res);
@@ -653,5 +636,5 @@
const MCTargetOptions &Options) {
const Triple &TT = STI.getTargetTriple();
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
- return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
+ return new RISCVAsmBackend(STI, MRI, OSABI, TT.isArch64Bit(), Options);
}
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