[PATCH] D141408: [CodeGen] Introduce a generic MEMBARRIER instruction [mostly-nfc]

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

In D141408#4041719 <https://reviews.llvm.org/D141408#4041719>, @lenary wrote:

> Broadly, this looks right. I'm glad stuff is finally moving on changes in this direction.
>
> Why does this barrier not need an ordering, but ARM/AArch64 do? Some of the targets in this patch still have weak memory orderings (RISC-V). Is the plan to update the MEMBARRIER with the ordering later, in a way that won't actually affect the selection for these targets so far?

I am working incrementally so that each patch is self contained, with as few test deltas as I can manage.  As I said in the commit comment, this is merely staging, not a inherent disagreement on the result.

I've taken a quick look at ARM/AArch64 and don't see optimizations actually using the order on their compiler_barrier.  We do have one backend which does, but that's AMDGPU which doesn't distinguish between a membarrier and a atomic_fence until late expansion.


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  https://reviews.llvm.org/D141408/new/

https://reviews.llvm.org/D141408