[PATCH] D141408: [CodeGen] Introduce a generic MEMBARRIER instruction [mostly-nfc]

[Sam Elliott via Phabricator via llvm-commits]

lenary added a comment.

Broadly, this looks right. I'm glad stuff is finally moving on changes in this direction.

Why does this barrier not need an ordering, but ARM/AArch64 do? Some of the targets in this patch still have weak memory orderings (RISC-V). Is the plan to update the MEMBARRIER with the ordering later, in a way that won't actually affect the selection for these targets so far?


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  https://reviews.llvm.org/D141408/new/

https://reviews.llvm.org/D141408