[PATCH] D141419: [DAGCombine] Suppress some foldings of rounding to fp16

[Phoebe Wang via Phabricator via llvm-commits]

pengfei added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:16274-16275
+    // from f32.  Suppress this folding in both the scalar and vector forms.
+    bool TargIsFp16 = VT == MVT::f16 ||
+                      (VT.isVector() && VT.getVectorElementType() == MVT::f16);
+    if (TargIsFp16) {
----------------
This equals to `VT.getScalarType() == MVT::f16`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141419/new/

https://reviews.llvm.org/D141419