[PATCH] D141043: [AArch64][SVE] Avoid AND operation if both side are splat of i1 or PTRUE

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16324-16326
+  SDValue Op = N->getOperand(0);
+  while (Op.getOpcode() == AArch64ISD::REINTERPRET_CAST)
+    Op = Op->getOperand(0);
----------------
This code would simplify:

  t0: nxv2i1 ...
    t1: nxv16i1 REINTERPRET_CAST t0
      t2: nxv4i1 REINTERPRET_CAST t1
        t3: nxv8i1 REINTERPRET_CAST t2
          t4: nxv2i1 REINTERPRET_CAST t3

into: `t0`

But not something like this 

  t0: nxv2i1 ...
    t1: nxv16i1 REINTERPRET_CAST t0
      t2: nxv4i1 REINTERPRET_CAST t1
        t3: nxv8i1 REINTERPRET_CAST t2
          t4: nxv16i1 REINTERPRET_CAST t3

into:

  t0: nxv2i1 ...
    t1: nxv16i1 REINTERPRET_CAST t0

I'm not sure if this is common, but it's probably more robust to do something like this:

  while(Op.getOpcode() == AArch64ISD::REINTERPRET_CAST &&
        LeafOp.getValueType() != Op.getValueType())
    Op = Op->getOperand(0);




================
Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll:128
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    ptrue p1.d
-; CHECK-NEXT:    and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    ret
----------------
Nice :)


================
Comment at: llvm/test/CodeGen/AArch64/sve-splat-one-and-ptrue.ll:8
+
+define <vscale x 16 x i1> @foo() #0 {
+; CHECK-LABEL: foo:
----------------
Can you give these tests more meaningful names, e.g. `@fold_away_ptrue_and_ptrue` for `@foo` and `@fold_away_ptrue_and_splat_predicate` for `bar`.




CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141043/new/

https://reviews.llvm.org/D141043