[PATCH] D141311: [RISCV] Avoid emitting hardware fences for singlethread fences

Mon Jan 9 11:43:07 PST 2023

jrtc27 added a comment.

In D141311#4037302 <https://reviews.llvm.org/D141311#4037302>, @reames wrote:

> In D141311#4037290 <https://reviews.llvm.org/D141311#4037290>, @jrtc27 wrote:
>
>> If every backend is doing it shouldn't this be a generic thing rather than copy/pasted to every backend?
>
> Agreed.  I looked briefly at doing this.  I think we could probably share the SDAG pieces; the pseudos look less obvious.  Happy to take a pass at this, but I'd prefer that be non-blocking for this change.  You okay with that?

Yeah, I just wish it were done that way from the start :( busywork as a result

================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1849
+let hasSideEffects = 1, isMeta = 1 in
+def Int_MemBarrier : Pseudo<(outs), (ins),
+                     [(RISCVMemBarrier)]>;
----------------
reames wrote:
> jrtc27 wrote:
> > This isn't standard naming for pseudos, but maybe other backends do it this way too?...
> I honestly copied this from X86 without trying to understand it closely.  If you have suggestions, happy to apply them.  
Normally it'd be riscv_membarrier defined at the top of the file and PseudoMEMBARRIER defined here (or in the instructions section)

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141311/new/

https://reviews.llvm.org/D141311