[PATCH] D141043: [AArch64][SVE] Avoid AND operation if both side are splat of i1 or PTRUE

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sve-splat-one-and-ptrue.ll:40
+; CHECK-NEXT:    ptrue p1.d
+; CHECK-NEXT:    ptrue p2.s
+; CHECK-NEXT:    and p0.b, p0/z, p0.b, p1.b
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sdesmalen wrote:
> I would have expected all ptrues to have folded away and to only have:
> 
>   ptrue p0.s
> 
> Why are these AND instructions not removed?
In second consideration, I see that only one of these AND's can be removed. The semantics of llvm.aarch64.sve.convert.to.svbool.nxv2i1 are such that it explicitly zeroes the inactive lanes, i.e. they don't map 1-1 to REINTERPRET_CAST.


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  https://reviews.llvm.org/D141043/new/

https://reviews.llvm.org/D141043