[PATCH] D141043: [AArch64][SVE] Avoid AND operation if both side are splat of i1 or PTRUE

[David Sherwood via Phabricator via llvm-commits]

david-arm added a comment.

Hi @dtemirbulatov, this is looking better now thanks! I just have a couple more comments ...



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16310
 
+  // If both sides of AND operations are i1 splat_vectors then
+  // we can produce just i1 splat_vector as the result.
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I think this comment suggests we only support the case where both operands are i1 splat_vectors, but your code below supports only one operand being an all-active predicate. Can you update the comment to reflect that? For example, something like

  // If either side of the AND operation is a i1 splat_vector then return the other
  // operand.

For example, `and %splat_i1, %b` -> `%b` and `and %a, %splat_i1` -> `%a`. Can you add twmo test cases to cover both of these cases too?


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Comment at: llvm/test/CodeGen/AArch64/sve-splat-one-and-ptrue.ll:35
+
+define <vscale x 16 x i1> @foo1() #0 {
+; CHECK-LABEL: foo1:
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This looks like a negative test. Can you add a comment explaining why the DAG combine doesn't happen?


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