[PATCH] D141213: Add an AArch64 DAG combine to eliminate unnecessary XTN operations when truncating v1i64 to v1i32.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17477
+      SDLoc DL(N);
+      return DAG.getNode(ISD::BITCAST, DL, VT, N0.getOperand(0));
+    }
----------------
Put `SDLoc(N)` into the argument list.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141213/new/

https://reviews.llvm.org/D141213