[PATCH] D141213: Add an AArch64 DAG combine to eliminate unnecessary XTN operations when truncating v1i64 to v1i32.

[Owen Anderson via Phabricator via llvm-commits]

resistor created this revision.
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Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141213

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/trunc-v1i64.ll


Index: llvm/test/CodeGen/AArch64/trunc-v1i64.ll
===================================================================
--- llvm/test/CodeGen/AArch64/trunc-v1i64.ll
+++ llvm/test/CodeGen/AArch64/trunc-v1i64.ll
@@ -8,12 +8,9 @@
 ; scalarization will cause an assertion failure, as v1i64 is a legal type in
 ; AArch64. We change the default behaviour from be scalarized to be widen.
 
-; FIXME: Currently XTN is generated for v1i32, but it can be optimized.
-; Just like v1i16 and v1i8, there is no XTN generated.
-
 define <2 x i32> @test_v1i32_0(<1 x i64> %in0) {
 ; CHECK-LABEL: test_v1i32_0:
-; CHECK: xtn v0.2s, v0.2d
+; CHECK-NOT: xtn
   %1 = shufflevector <1 x i64> %in0, <1 x i64> undef, <2 x i32> <i32 0, i32 undef>
   %2 = trunc <2 x i64> %1 to <2 x i32>
   ret <2 x i32> %2
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -17462,6 +17462,22 @@
     return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, Op);
   }
 
+  // (v2i32 trunc (v2i64 concat_vectors x, undef)) -> (bitcast x, v2i32)
+  if (N0.getOpcode() == ISD::CONCAT_VECTORS && N0.getValueType() == MVT::v2i64) {
+    bool AllButFirstUndef = true;
+    for (unsigned i = 1, e = N0.getNumOperands(); i < e; ++i) {
+      if (!N0.getOperand(i).isUndef()) {
+        AllButFirstUndef = false;
+        break;
+      }
+    }
+
+    if (AllButFirstUndef) {
+      SDLoc DL(N);
+      return DAG.getNode(ISD::BITCAST, DL, VT, N0.getOperand(0));
+    }
+  }
+
   return SDValue();
 }
 


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