[llvm] 1b12d7d - [AMDGPU] Combine redundant Asm64 and AsmVOP3DPPBase. NFC
Joe Nash via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 6 11:09:56 PST 2023
Author: Joe Nash
Date: 2023-01-06T14:09:42-05:00
New Revision: 1b12d7d15b4f3238d5d09efcfc0cc8fde58bddb1
URL: https://github.com/llvm/llvm-project/commit/1b12d7d15b4f3238d5d09efcfc0cc8fde58bddb1
DIFF: https://github.com/llvm/llvm-project/commit/1b12d7d15b4f3238d5d09efcfc0cc8fde58bddb1.diff
LOG: [AMDGPU] Combine redundant Asm64 and AsmVOP3DPPBase. NFC
Reduce duplication in the codebase by combining these fields in
VOPProfile.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D141088
Added:
Modified:
llvm/lib/Target/AMDGPU/SIInstrInfo.td
llvm/lib/Target/AMDGPU/VOP1Instructions.td
llvm/lib/Target/AMDGPU/VOP2Instructions.td
llvm/lib/Target/AMDGPU/VOP3PInstructions.td
llvm/lib/Target/AMDGPU/VOPCInstructions.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 6e13074aa38a1..887aa3adaa7eb 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -2099,8 +2099,7 @@ class getOutsSDWA <bit HasDst, ValueType DstVT, RegisterOperand DstRCSDWA> {
}
// Returns the assembly string for the inputs and outputs of a VOP[12C]
-// instruction. This does not add the _e32 suffix, so it can be reused
-// by getAsm64.
+// instruction.
class getAsm32 <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> {
string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
string src0 = ", $src0";
@@ -2121,23 +2120,6 @@ class getAsmVOPDPart <int NumSrcArgs, string XorY> {
!if(!ge(NumSrcArgs, 2), src1, "");
}
-// Returns the assembly string for the inputs and outputs of a VOP3
-// instruction.
-class getAsm64 <bit HasDst, int NumSrcArgs, bit HasIntClamp, bit HasModifiers,
- bit HasOMod, ValueType DstVT = i32> {
- string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
- string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
- string src1 = !if(!eq(NumSrcArgs, 1), "",
- !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
- " $src1_modifiers,"));
- string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
- string iclamp = !if(HasIntClamp, "$clamp", "");
- string ret =
- !if(!not(HasModifiers),
- getAsm32<HasDst, NumSrcArgs, DstVT>.ret # iclamp,
- dst#", "#src0#src1#src2#"$clamp"#!if(HasOMod, "$omod", ""));
-}
-
// Returns the assembly string for the inputs and outputs of a VOP3P
// instruction.
class getAsmVOP3P <int NumSrcArgs, bit HasModifiers,
@@ -2212,7 +2194,7 @@ class getAsmDPP8 <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT
let ret = dst#args#" $dpp8$fi";
}
-class getAsmVOP3DPPBase <int NumSrcArgs, bit HasDst, bit HasClamp,
+class getAsmVOP3Base <int NumSrcArgs, bit HasDst, bit HasClamp,
bit HasOpSel, bit HasOMod, bit IsVOP3P,
bit HasModifiers, bit Src0HasMods,
bit Src1HasMods, bit Src2HasMods, ValueType DstVT = i32> {
@@ -2244,7 +2226,7 @@ class getAsmVOP3DPPBase <int NumSrcArgs, bit HasDst, bit HasClamp,
string clamp = !if(HasClamp, "$clamp", "");
string omod = !if(HasOMod, "$omod", "");
- string ret = dst#", "#src0#src1#src2#opsel#3PMods#clamp#omod;
+ string ret = dst#!if(!gt(NumSrcArgs,0),", "#src0#src1#src2#opsel#3PMods#clamp#omod, "");
}
@@ -2571,26 +2553,26 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> {
field string Asm32 = getAsm32<HasDst, NumSrcArgs, DstVT>.ret;
- field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasIntClamp, HasModifiers, HasOMod, DstVT>.ret;
- field string AsmVOP3P = getAsmVOP3P<NumSrcArgs, HasModifiers, HasClamp, HasOpSel>.ret;
- field string AsmVOP3OpSel = getAsmVOP3OpSel<NumSrcArgs,
- HasClamp,
- HasOMod,
- HasSrc0FloatMods,
- HasSrc1FloatMods,
- HasSrc2FloatMods>.ret;
field string AsmDPP = !if(HasExtDPP,
getAsmDPP<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret, "");
field string AsmDPP16 = getAsmDPP16<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret;
// DPP8 encoding has no fields for modifiers, and it is enforced by setting
// the asm operand name via this HasModifiers flag
field string AsmDPP8 = getAsmDPP8<HasDst, NumSrcArgs, 0 /*HasModifiers*/, DstVT>.ret;
- field string AsmVOP3DPPBase = getAsmVOP3DPPBase<NumSrcArgs, HasDst, HasClamp,
+ field string AsmVOP3Base = getAsmVOP3Base<NumSrcArgs, HasDst, HasClamp,
HasOpSel, HasOMod, IsVOP3P, HasModifiers, HasModifiers, HasModifiers,
HasModifiers, DstVT>.ret;
- field string AsmVOP3DPP = getAsmVOP3DPP<AsmVOP3DPPBase>.ret;
- field string AsmVOP3DPP16 = getAsmVOP3DPP16<AsmVOP3DPPBase>.ret;
- field string AsmVOP3DPP8 = getAsmVOP3DPP8<AsmVOP3DPPBase>.ret;
+ field string Asm64 = AsmVOP3Base;
+ field string AsmVOP3P = getAsmVOP3P<NumSrcArgs, HasModifiers, HasClamp, HasOpSel>.ret;
+ field string AsmVOP3OpSel = getAsmVOP3OpSel<NumSrcArgs,
+ HasClamp,
+ HasOMod,
+ HasSrc0FloatMods,
+ HasSrc1FloatMods,
+ HasSrc2FloatMods>.ret;
+ field string AsmVOP3DPP = getAsmVOP3DPP<AsmVOP3Base>.ret;
+ field string AsmVOP3DPP16 = getAsmVOP3DPP16<AsmVOP3Base>.ret;
+ field string AsmVOP3DPP8 = getAsmVOP3DPP8<AsmVOP3Base>.ret;
field string AsmSDWA = getAsmSDWA<HasDst, NumSrcArgs, DstVT>.ret;
field string AsmSDWA9 = getAsmSDWA9<HasDst, HasSDWAOMod, NumSrcArgs, DstVT>.ret;
field string AsmVOPDX = getAsmVOPDPart<NumSrcArgs, "X">.ret;
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index 85db94bff7640..285499ad6984f 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -163,8 +163,7 @@ class VOPProfileI2F<ValueType dstVt, ValueType srcVt> :
let Ins64 = (ins Src0RC64:$src0, clampmod:$clamp, omod:$omod);
let InsVOP3Base = (ins Src0VOP3DPP:$src0, clampmod:$clamp, omod:$omod);
- let Asm64 = "$vdst, $src0$clamp$omod";
- let AsmVOP3DPPBase = Asm64;
+ let AsmVOP3Base = "$vdst, $src0$clamp$omod";
let HasModifiers = 0;
let HasClamp = 1;
@@ -175,8 +174,7 @@ class VOPProfileI2F_True16<ValueType dstVt, ValueType srcVt> :
let Ins64 = (ins Src0RC64:$src0, clampmod:$clamp, omod:$omod);
let InsVOP3Base = (ins Src0VOP3DPP:$src0, clampmod:$clamp, omod:$omod);
- let Asm64 = "$vdst, $src0$clamp$omod";
- let AsmVOP3DPPBase = Asm64;
+ let AsmVOP3Base = "$vdst, $src0$clamp$omod";
let HasModifiers = 0;
let HasClamp = 1;
@@ -382,7 +380,6 @@ class VOP_MOVREL<RegisterOperand Src1RC> : VOPProfile<[untyped, i32, untyped, un
let Ins32 = (ins Src0RC32:$vdst, Src1RC:$src0);
let Ins64 = (ins Src0RC64:$vdst, Src1RC:$src0);
let Asm32 = getAsm32<1, 1>.ret;
- let Asm64 = getAsm64<1, 1, 0, 0, 1>.ret;
let OutsSDWA = (outs Src0RC32:$vdst);
let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
@@ -403,8 +400,8 @@ class VOP_MOVREL<RegisterOperand Src1RC> : VOPProfile<[untyped, i32, untyped, un
let InsVOP3DPP16 = getInsVOP3DPP16<InsVOP3Base, Src0RC64, NumSrcArgs>.ret;
let InsVOP3DPP8 = getInsVOP3DPP8<InsVOP3Base, Src0RC64, NumSrcArgs>.ret;
- let AsmVOP3DPPBase =
- getAsmVOP3DPPBase<NumSrcArgs, 1 /* HasDst */, HasClamp,
+ let AsmVOP3Base =
+ getAsmVOP3Base<NumSrcArgs, 1 /* HasDst */, HasClamp,
HasOpSel, HasOMod, IsVOP3P, HasModifiers,
HasModifiers, HasModifiers, HasModifiers>.ret;
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 4dd4564092196..636c46702696f 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -448,14 +448,13 @@ class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, v
dst_sel:$dst_sel, dst_unused:$dst_unused,
src0_sel:$src0_sel, src1_sel:$src1_sel);
let Asm32 = getAsm32<1, 2, vt0>.ret;
- let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, vt0>.ret;
let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt0>.ret;
let AsmDPP16 = getAsmDPP16<1, 2, HasModifiers, vt0>.ret;
let AsmDPP8 = getAsmDPP8<1, 2, 0, vt0>.ret;
let AsmSDWA = getAsmSDWA<1, 2, vt0>.ret;
let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt0>.ret;
- let AsmVOP3DPPBase =
- getAsmVOP3DPPBase<2 /*NumSrcArgs*/, HasDst, HasClamp,
+ let AsmVOP3Base =
+ getAsmVOP3Base<2 /*NumSrcArgs*/, HasDst, HasClamp,
HasOpSel, HasOMod, IsVOP3P, HasModifiers,
HasModifiers, HasModifiers,
0 /*Src2HasMods*/, DstVT>.ret;
@@ -535,13 +534,12 @@ def VOP_DOT_ACC_I32_I32 : VOP_DOT_ACC<i32, i32> {
// Write out to vcc or arbitrary SGPR.
def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], /*EnableClamp=*/1> {
let Asm32 = "$vdst, vcc, $src0, $src1";
- let Asm64 = "$vdst, $sdst, $src0, $src1$clamp";
+ let AsmVOP3Base = "$vdst, $sdst, $src0, $src1$clamp";
let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
let AsmDPP8 = "$vdst, vcc, $src0, $src1 $dpp8$fi";
let AsmDPP16 = AsmDPP#"$fi";
- let AsmVOP3DPPBase = Asm64;
let InsDPP = (ins DstRCDPP:$old,
Src0DPP:$src0,
Src1DPP:$src1,
@@ -563,7 +561,6 @@ def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], /*EnableClamp=*/
def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableClamp=*/1> {
let HasSrc2Mods = 0;
let Asm32 = "$vdst, vcc, $src0, $src1, vcc";
- let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
@@ -571,7 +568,7 @@ def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableClamp=*/1>
let AsmDPP16 = AsmDPP#"$fi";
let Outs32 = (outs DstRC:$vdst);
let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
- let AsmVOP3DPPBase = Asm64;
+ let AsmVOP3Base = "$vdst, $sdst, $src0, $src1, $src2$clamp";
let OutsVOP3DPP = Outs64;
let OutsVOP3DPP8 = Outs64;
@@ -606,13 +603,12 @@ def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableClamp=*/1>
// Read in from vcc or arbitrary SGPR.
class VOP2e_SGPR<list<ValueType> ArgVT> : VOPProfile<ArgVT> {
let Asm32 = "$vdst, $src0, $src1";
- let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2";
let AsmSDWA = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
let AsmSDWA9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
let AsmDPP = "$vdst, $src0_modifiers, $src1_modifiers, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
let AsmDPP8 = "$vdst, $src0, $src1, vcc $dpp8$fi";
let AsmDPP16 = AsmDPP#"$fi";
- let AsmVOP3DPPBase = Asm64;
+ let AsmVOP3Base = "$vdst, $src0_modifiers, $src1_modifiers, $src2";
let Outs32 = (outs DstRC:$vdst);
let Outs64 = (outs DstRC:$vdst);
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index e33ba7acd03a3..5b8b0258cb823 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -17,7 +17,7 @@ class VOP3P_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR,
// We do not want to print src modifiers for vop3p because the bits are
// overloaded in meaning and the logic in printOperandAndFPInputMods is
// wrong for vop3p
- let AsmVOP3DPPBase = AsmVOP3P;
+ let AsmVOP3Base = AsmVOP3P;
}
// Used for FMA_MIX* and MAD_MIX* insts
@@ -50,9 +50,8 @@ class VOP3P_Mix_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR,
// due to the logic in class VOP3_Pseudo
let Ins64 = !con(srcs, mods);
let InsVOP3Base = !con(dpp_srcs, mods);
- let Asm64 =
+ let AsmVOP3Base =
"$vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$op_sel$op_sel_hi$clamp";
- let AsmVOP3DPPBase = Asm64;
}
multiclass VOP3PInst<string OpName, VOPProfile P,
@@ -454,8 +453,7 @@ class VOPProfileMAI<VOPProfile P, RegisterOperand _SrcRC, RegisterOperand _DstRC
let HasIntClamp = 0;
let HasOMod = 0;
let HasModifiers = 0;
- let Asm64 = "$vdst, $src0, $src1, $src2$cbsz$abid$blgp";
- let AsmVOP3DPPBase = Asm64;
+ let AsmVOP3Base = "$vdst, $src0, $src1, $src2$cbsz$abid$blgp";
let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, Src2RC64:$src2, cbsz:$cbsz, abid:$abid, blgp:$blgp);
let InsVOP3Base = Ins64;
// Dst and SrcC cannot partially overlap if SrcC/Dst is bigger than 4 VGPRs.
diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
index a588b11d871db..439ca40ae3fb2 100644
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -108,9 +108,8 @@ class VOPC_NoSdst_Profile<list<SchedReadWrite> sched, ValueType vt0,
let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
src0_sel:$src0_sel, src1_sel:$src1_sel);
- let Asm64 = !if(isFloatType<Src0VT>.ret, "$src0_modifiers, $src1_modifiers$clamp",
+ let AsmVOP3Base = !if(isFloatType<Src0VT>.ret, "$src0_modifiers, $src1_modifiers$clamp",
"$src0, $src1");
- let AsmVOP3DPPBase = Asm64;
let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel";
let EmitDst = 0;
}
@@ -774,8 +773,7 @@ class VOPC_Class_Profile<list<SchedReadWrite> sched, ValueType src0VT, ValueType
dag InsPartVOP3DPP = (ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0, VGPRSrc_32:$src1);
let InsVOP3Base = !con(InsPartVOP3DPP, !if(HasOpSel, (ins op_sel0:$op_sel),
(ins)));
- let Asm64 = "$sdst, $src0_modifiers, $src1";
- let AsmVOP3DPPBase = Asm64;
+ let AsmVOP3Base = "$sdst, $src0_modifiers, $src1";
let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
@@ -809,8 +807,7 @@ class VOPC_Class_NoSdst_Profile<list<SchedReadWrite> sched, ValueType src0VT, Va
let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
src0_sel:$src0_sel, src1_sel:$src1_sel);
- let Asm64 = "$src0_modifiers, $src1";
- let AsmVOP3DPPBase = Asm64;
+ let AsmVOP3Base = "$src0_modifiers, $src1";
let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel";
let EmitDst = 0;
}
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