[PATCH] D140347: SelectionDAG: Teach ComputeKnownBits about VSCALE

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D140347#4030800 <https://reviews.llvm.org/D140347#4030800>, @foad wrote:

>> I think the multiplier can be negative (see the _with_negative_multiplier tests).
>
> This needs documenting. Speciflcally, for the ISD::VSCALE node, if the output is wider than the input, does it zero- or sign-extend the input? (Or to put it another way, does it do an unsigned extending multiply or a signed extending multiply?)

I'm not sure it's allowed to have a different type. In tablegen it is using `SDTIntUnaryOp` which requires the input and output types to match.


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