[llvm] 1aa9862 - [RISCV] Add more XVentanaCondOps patterns.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 6 08:29:35 PST 2023
Author: Craig Topper
Date: 2023-01-06T08:29:23-08:00
New Revision: 1aa9862df3634d1d526e5bfd0431408a24ac435a
URL: https://github.com/llvm/llvm-project/commit/1aa9862df3634d1d526e5bfd0431408a24ac435a
DIFF: https://github.com/llvm/llvm-project/commit/1aa9862df3634d1d526e5bfd0431408a24ac435a.diff
LOG: [RISCV] Add more XVentanaCondOps patterns.
Add patterns with seteq/setne conditions.
We don't have instructions for seteq/setne except for comparing
with zero and need to emit an ADDI or XOR before a seqz/snez to
compare other values.
The select ISD node takes a 0/1 value for the condition, but the
VT_MASKC(N) instructions check all XLen bits for zero or non-zero.
We can use this to avoid the seqz/snez in many cases.
This is pretty ridiculous number of patterns. I wonder if we could
use some ComplexPatterns to merge them, but I'd like to do that as
a follow up and focus on correctness of the result in this patch.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D140421
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
llvm/test/CodeGen/RISCV/select.ll
llvm/test/CodeGen/RISCV/xventanacondops.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
index 18d6515f39d4..68c3a2105373 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
@@ -35,6 +35,42 @@ def : Pat<(select GPR:$rc, GPR:$rs1, (i64 0)),
def : Pat<(select GPR:$rc, (i64 0), GPR:$rs1),
(VT_MASKCN $rs1, $rc)>;
+def : Pat<(select (i64 (setne GPR:$rc, (i64 0))), GPR:$rs1, (i64 0)),
+ (VT_MASKC GPR:$rs1, GPR:$rc)>;
+def : Pat<(select (i64 (seteq GPR:$rc, (i64 0))), GPR:$rs1, (i64 0)),
+ (VT_MASKCN GPR:$rs1, GPR:$rc)>;
+def : Pat<(select (i64 (setne GPR:$rc, (i64 0))), (i64 0), GPR:$rs1),
+ (VT_MASKCN GPR:$rs1, GPR:$rc)>;
+def : Pat<(select (i64 (seteq GPR:$rc, (i64 0))), (i64 0), GPR:$rs1),
+ (VT_MASKC GPR:$rs1, GPR:$rc)>;
+
+def : Pat<(select (i64 (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, (i64 0)),
+ (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
+def : Pat<(select (i64 (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs1, (i64 0)),
+ (VT_MASKCN GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
+def : Pat<(select (i64 (setne GPR:$x, simm12_plus1:$y)), (i64 0), GPR:$rs1),
+ (VT_MASKCN GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
+def : Pat<(select (i64 (seteq GPR:$x, simm12_plus1:$y)), (i64 0), GPR:$rs1),
+ (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
+
+def : Pat<(select (i64 (setne GPR:$x, (i64 -2048))), GPR:$rs1, (i64 0)),
+ (VT_MASKC GPR:$rs1, (XORI GPR:$x, -2048))>;
+def : Pat<(select (i64 (seteq GPR:$x, (i64 -2048))), GPR:$rs1, (i64 0)),
+ (VT_MASKCN GPR:$rs1, (XORI GPR:$x, -2048))>;
+def : Pat<(select (i64 (setne GPR:$x, (i64 -2048))), (i64 0), GPR:$rs1),
+ (VT_MASKCN GPR:$rs1, (XORI GPR:$x, -2048))>;
+def : Pat<(select (i64 (seteq GPR:$x, (i64 -2048))), (i64 0), GPR:$rs1),
+ (VT_MASKC GPR:$rs1, (XORI GPR:$x, -2048))>;
+
+def : Pat<(select (i64 (setne GPR:$x, GPR:$y)), GPR:$rs1, (i64 0)),
+ (VT_MASKC GPR:$rs1, (XOR GPR:$x, GPR:$y))>;
+def : Pat<(select (i64 (seteq GPR:$x, GPR:$y)), GPR:$rs1, (i64 0)),
+ (VT_MASKCN GPR:$rs1, (XOR GPR:$x, GPR:$y))>;
+def : Pat<(select (i64 (setne GPR:$x, GPR:$y)), (i64 0), GPR:$rs1),
+ (VT_MASKCN GPR:$rs1, (XOR GPR:$x, GPR:$y))>;
+def : Pat<(select (i64 (seteq GPR:$x, GPR:$y)), (i64 0), GPR:$rs1),
+ (VT_MASKC GPR:$rs1, (XOR GPR:$x, GPR:$y))>;
+
// Conditional AND operation patterns.
def : Pat<(i64 (select GPR:$rc, (and GPR:$rs1, GPR:$rs2), GPR:$rs1)),
(OR (AND $rs1, $rs2), (VT_MASKCN $rs1, $rc))>;
@@ -44,4 +80,31 @@ def : Pat<(i64 (select GPR:$rc, GPR:$rs1, (and GPR:$rs1, GPR:$rs2))),
// Basic select pattern that selects between 2 registers.
def : Pat<(i64 (select GPR:$rc, GPR:$rs1, GPR:$rs2)),
(OR (VT_MASKC $rs1, $rc), (VT_MASKCN $rs2, $rc))>;
+
+def : Pat<(i64 (select (i64 (setne GPR:$rc, (i64 0))), GPR:$rs1, GPR:$rs2)),
+ (OR (VT_MASKC GPR:$rs1, GPR:$rc), (VT_MASKCN GPR:$rs2, GPR:$rc))>;
+def : Pat<(i64 (select (i64 (seteq GPR:$rc, (i64 0))), GPR:$rs2, GPR:$rs1)),
+ (OR (VT_MASKC GPR:$rs1, GPR:$rc), (VT_MASKCN GPR:$rs2, GPR:$rc))>;
+
+def : Pat<(i64 (select (i64 (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, GPR:$rs2)),
+ (OR (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y))),
+ (VT_MASKCN GPR:$rs2, (ADDI GPR:$x, (NegImm simm12_plus1:$y))))>;
+def : Pat<(i64 (select (i64 (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs2, GPR:$rs1)),
+ (OR (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y))),
+ (VT_MASKCN GPR:$rs2, (ADDI GPR:$x, (NegImm simm12_plus1:$y))))>;
+
+def : Pat<(i64 (select (i64 (setne GPR:$x, (i64 -2048))), GPR:$rs1, GPR:$rs2)),
+ (OR (VT_MASKC GPR:$rs1, (XORI GPR:$x, -2048)),
+ (VT_MASKCN GPR:$rs2, (XORI GPR:$x, -2048)))>;
+def : Pat<(i64 (select (i64 (seteq GPR:$x, (i64 -2048))), GPR:$rs2, GPR:$rs1)),
+ (OR (VT_MASKC GPR:$rs1, (XORI GPR:$x, -2048)),
+ (VT_MASKCN GPR:$rs2, (XORI GPR:$x, -2048)))>;
+
+def : Pat<(i64 (select (i64 (setne GPR:$x, GPR:$y)), GPR:$rs1, GPR:$rs2)),
+ (OR (VT_MASKC GPR:$rs1, (XOR GPR:$x, GPR:$y)),
+ (VT_MASKCN GPR:$rs2, (XOR GPR:$x, GPR:$y)))>;
+def : Pat<(i64 (select (i64 (seteq GPR:$x, GPR:$y)), GPR:$rs2, GPR:$rs1)),
+ (OR (VT_MASKC GPR:$rs1, (XOR GPR:$x, GPR:$y)),
+ (VT_MASKCN GPR:$rs2, (XOR GPR:$x, GPR:$y)))>;
+
} // Predicates = [IsRV64, HasVendorXVentanaCondOps]
diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll
index 2e9c4e7df1d0..acc441af049e 100644
--- a/llvm/test/CodeGen/RISCV/select.ll
+++ b/llvm/test/CodeGen/RISCV/select.ll
@@ -138,9 +138,8 @@ define i16 @select_xor_3(i16 %A, i8 %cond) {
; CONDOPS-LABEL: select_xor_3:
; CONDOPS: # %bb.0: # %entry
; CONDOPS-NEXT: andi a1, a1, 1
-; CONDOPS-NEXT: seqz a1, a1
; CONDOPS-NEXT: li a2, 43
-; CONDOPS-NEXT: vt.maskc a1, a2, a1
+; CONDOPS-NEXT: vt.maskcn a1, a2, a1
; CONDOPS-NEXT: xor a0, a0, a1
; CONDOPS-NEXT: ret
entry:
@@ -205,8 +204,7 @@ define i32 @select_xor_4(i32 %A, i32 %B, i8 %cond) {
; CONDOPS-LABEL: select_xor_4:
; CONDOPS: # %bb.0: # %entry
; CONDOPS-NEXT: andi a2, a2, 1
-; CONDOPS-NEXT: seqz a2, a2
-; CONDOPS-NEXT: vt.maskc a1, a1, a2
+; CONDOPS-NEXT: vt.maskcn a1, a1, a2
; CONDOPS-NEXT: xor a0, a0, a1
; CONDOPS-NEXT: ret
entry:
@@ -384,8 +382,7 @@ define i32 @select_or_2(i32 %A, i32 %B, i8 %cond) {
; CONDOPS-LABEL: select_or_2:
; CONDOPS: # %bb.0: # %entry
; CONDOPS-NEXT: andi a2, a2, 1
-; CONDOPS-NEXT: seqz a2, a2
-; CONDOPS-NEXT: vt.maskc a1, a1, a2
+; CONDOPS-NEXT: vt.maskcn a1, a1, a2
; CONDOPS-NEXT: or a0, a0, a1
; CONDOPS-NEXT: ret
entry:
@@ -449,8 +446,7 @@ define i32 @select_or_3(i32 %A, i32 %B, i32 %cond) {
; CONDOPS-LABEL: select_or_3:
; CONDOPS: # %bb.0: # %entry
; CONDOPS-NEXT: andi a2, a2, 1
-; CONDOPS-NEXT: seqz a2, a2
-; CONDOPS-NEXT: vt.maskc a1, a1, a2
+; CONDOPS-NEXT: vt.maskcn a1, a1, a2
; CONDOPS-NEXT: or a0, a0, a1
; CONDOPS-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/xventanacondops.ll b/llvm/test/CodeGen/RISCV/xventanacondops.ll
index 046d56e021b7..c00a7d2e9b7c 100644
--- a/llvm/test/CodeGen/RISCV/xventanacondops.ll
+++ b/llvm/test/CodeGen/RISCV/xventanacondops.ll
@@ -236,9 +236,8 @@ define i64 @seteq(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: seteq:
; CHECK: # %bb.0:
; CHECK-NEXT: xor a0, a0, a1
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: vt.maskcn a1, a3, a0
-; CHECK-NEXT: vt.maskc a0, a2, a0
+; CHECK-NEXT: vt.maskcn a1, a2, a0
+; CHECK-NEXT: vt.maskc a0, a3, a0
; CHECK-NEXT: or a0, a0, a1
; CHECK-NEXT: ret
%rc = icmp eq i64 %a, %b
@@ -250,7 +249,6 @@ define i64 @setne(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: setne:
; CHECK: # %bb.0:
; CHECK-NEXT: xor a0, a0, a1
-; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vt.maskcn a1, a3, a0
; CHECK-NEXT: vt.maskc a0, a2, a0
; CHECK-NEXT: or a0, a0, a1
@@ -367,10 +365,9 @@ define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
define i64 @seteq_zero(i64 %a, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: seteq_zero:
; CHECK: # %bb.0:
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: vt.maskcn a2, a2, a0
-; CHECK-NEXT: vt.maskc a0, a1, a0
-; CHECK-NEXT: or a0, a0, a2
+; CHECK-NEXT: vt.maskcn a1, a1, a0
+; CHECK-NEXT: vt.maskc a0, a2, a0
+; CHECK-NEXT: or a0, a0, a1
; CHECK-NEXT: ret
%rc = icmp eq i64 %a, 0
%sel = select i1 %rc, i64 %rs1, i64 %rs2
@@ -380,7 +377,6 @@ define i64 @seteq_zero(i64 %a, i64 %rs1, i64 %rs2) {
define i64 @setne_zero(i64 %a, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: setne_zero:
; CHECK: # %bb.0:
-; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vt.maskcn a2, a2, a0
; CHECK-NEXT: vt.maskc a0, a1, a0
; CHECK-NEXT: or a0, a0, a2
@@ -394,10 +390,9 @@ define i64 @seteq_constant(i64 %a, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: seteq_constant:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, a0, -123
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: vt.maskcn a2, a2, a0
-; CHECK-NEXT: vt.maskc a0, a1, a0
-; CHECK-NEXT: or a0, a0, a2
+; CHECK-NEXT: vt.maskcn a1, a1, a0
+; CHECK-NEXT: vt.maskc a0, a2, a0
+; CHECK-NEXT: or a0, a0, a1
; CHECK-NEXT: ret
%rc = icmp eq i64 %a, 123
%sel = select i1 %rc, i64 %rs1, i64 %rs2
@@ -408,7 +403,6 @@ define i64 @setne_constant(i64 %a, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: setne_constant:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, a0, -456
-; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vt.maskcn a2, a2, a0
; CHECK-NEXT: vt.maskc a0, a1, a0
; CHECK-NEXT: or a0, a0, a2
@@ -422,10 +416,9 @@ define i64 @seteq_neg2048(i64 %a, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: seteq_neg2048:
; CHECK: # %bb.0:
; CHECK-NEXT: xori a0, a0, -2048
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: vt.maskcn a2, a2, a0
-; CHECK-NEXT: vt.maskc a0, a1, a0
-; CHECK-NEXT: or a0, a0, a2
+; CHECK-NEXT: vt.maskcn a1, a1, a0
+; CHECK-NEXT: vt.maskc a0, a2, a0
+; CHECK-NEXT: or a0, a0, a1
; CHECK-NEXT: ret
%rc = icmp eq i64 %a, -2048
%sel = select i1 %rc, i64 %rs1, i64 %rs2
@@ -436,7 +429,6 @@ define i64 @setne_neg2048(i64 %a, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: setne_neg2048:
; CHECK: # %bb.0:
; CHECK-NEXT: xori a0, a0, -2048
-; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vt.maskcn a2, a2, a0
; CHECK-NEXT: vt.maskc a0, a1, a0
; CHECK-NEXT: or a0, a0, a2
@@ -450,8 +442,7 @@ define i64 @zero1_seteq(i64 %a, i64 %b, i64 %rs1) {
; CHECK-LABEL: zero1_seteq:
; CHECK: # %bb.0:
; CHECK-NEXT: xor a0, a0, a1
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: vt.maskc a0, a2, a0
+; CHECK-NEXT: vt.maskcn a0, a2, a0
; CHECK-NEXT: ret
%rc = icmp eq i64 %a, %b
%sel = select i1 %rc, i64 %rs1, i64 0
@@ -462,8 +453,7 @@ define i64 @zero2_seteq(i64 %a, i64 %b, i64 %rs1) {
; CHECK-LABEL: zero2_seteq:
; CHECK: # %bb.0:
; CHECK-NEXT: xor a0, a0, a1
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: vt.maskcn a0, a2, a0
+; CHECK-NEXT: vt.maskc a0, a2, a0
; CHECK-NEXT: ret
%rc = icmp eq i64 %a, %b
%sel = select i1 %rc, i64 0, i64 %rs1
@@ -474,7 +464,6 @@ define i64 @zero1_setne(i64 %a, i64 %b, i64 %rs1) {
; CHECK-LABEL: zero1_setne:
; CHECK: # %bb.0:
; CHECK-NEXT: xor a0, a0, a1
-; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vt.maskc a0, a2, a0
; CHECK-NEXT: ret
%rc = icmp ne i64 %a, %b
@@ -486,7 +475,6 @@ define i64 @zero2_setne(i64 %a, i64 %b, i64 %rs1) {
; CHECK-LABEL: zero2_setne:
; CHECK: # %bb.0:
; CHECK-NEXT: xor a0, a0, a1
-; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vt.maskcn a0, a2, a0
; CHECK-NEXT: ret
%rc = icmp ne i64 %a, %b
@@ -497,8 +485,7 @@ define i64 @zero2_setne(i64 %a, i64 %b, i64 %rs1) {
define i64 @zero1_seteq_zero(i64 %a, i64 %rs1) {
; CHECK-LABEL: zero1_seteq_zero:
; CHECK: # %bb.0:
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: vt.maskc a0, a1, a0
+; CHECK-NEXT: vt.maskcn a0, a1, a0
; CHECK-NEXT: ret
%rc = icmp eq i64 %a, 0
%sel = select i1 %rc, i64 %rs1, i64 0
@@ -508,8 +495,7 @@ define i64 @zero1_seteq_zero(i64 %a, i64 %rs1) {
define i64 @zero2_seteq_zero(i64 %a, i64 %rs1) {
; CHECK-LABEL: zero2_seteq_zero:
; CHECK: # %bb.0:
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: vt.maskcn a0, a1, a0
+; CHECK-NEXT: vt.maskc a0, a1, a0
; CHECK-NEXT: ret
%rc = icmp eq i64 %a, 0
%sel = select i1 %rc, i64 0, i64 %rs1
@@ -519,7 +505,6 @@ define i64 @zero2_seteq_zero(i64 %a, i64 %rs1) {
define i64 @zero1_setne_zero(i64 %a, i64 %rs1) {
; CHECK-LABEL: zero1_setne_zero:
; CHECK: # %bb.0:
-; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vt.maskc a0, a1, a0
; CHECK-NEXT: ret
%rc = icmp ne i64 %a, 0
@@ -530,7 +515,6 @@ define i64 @zero1_setne_zero(i64 %a, i64 %rs1) {
define i64 @zero2_setne_zero(i64 %a, i64 %rs1) {
; CHECK-LABEL: zero2_setne_zero:
; CHECK: # %bb.0:
-; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vt.maskcn a0, a1, a0
; CHECK-NEXT: ret
%rc = icmp ne i64 %a, 0
@@ -542,8 +526,7 @@ define i64 @zero1_seteq_constant(i64 %a, i64 %rs1) {
; CHECK-LABEL: zero1_seteq_constant:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, a0, 231
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: vt.maskc a0, a1, a0
+; CHECK-NEXT: vt.maskcn a0, a1, a0
; CHECK-NEXT: ret
%rc = icmp eq i64 %a, -231
%sel = select i1 %rc, i64 %rs1, i64 0
@@ -554,8 +537,7 @@ define i64 @zero2_seteq_constant(i64 %a, i64 %rs1) {
; CHECK-LABEL: zero2_seteq_constant:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, a0, -546
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: vt.maskcn a0, a1, a0
+; CHECK-NEXT: vt.maskc a0, a1, a0
; CHECK-NEXT: ret
%rc = icmp eq i64 %a, 546
%sel = select i1 %rc, i64 0, i64 %rs1
@@ -566,7 +548,6 @@ define i64 @zero1_setne_constant(i64 %a, i64 %rs1) {
; CHECK-LABEL: zero1_setne_constant:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, a0, -321
-; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vt.maskc a0, a1, a0
; CHECK-NEXT: ret
%rc = icmp ne i64 %a, 321
@@ -578,7 +559,6 @@ define i64 @zero2_setne_constant(i64 %a, i64 %rs1) {
; CHECK-LABEL: zero2_setne_constant:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, a0, 654
-; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vt.maskcn a0, a1, a0
; CHECK-NEXT: ret
%rc = icmp ne i64 %a, -654
@@ -590,8 +570,7 @@ define i64 @zero1_seteq_neg2048(i64 %a, i64 %rs1) {
; CHECK-LABEL: zero1_seteq_neg2048:
; CHECK: # %bb.0:
; CHECK-NEXT: xori a0, a0, -2048
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: vt.maskc a0, a1, a0
+; CHECK-NEXT: vt.maskcn a0, a1, a0
; CHECK-NEXT: ret
%rc = icmp eq i64 %a, -2048
%sel = select i1 %rc, i64 %rs1, i64 0
@@ -602,8 +581,7 @@ define i64 @zero2_seteq_neg2048(i64 %a, i64 %rs1) {
; CHECK-LABEL: zero2_seteq_neg2048:
; CHECK: # %bb.0:
; CHECK-NEXT: xori a0, a0, -2048
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: vt.maskcn a0, a1, a0
+; CHECK-NEXT: vt.maskc a0, a1, a0
; CHECK-NEXT: ret
%rc = icmp eq i64 %a, -2048
%sel = select i1 %rc, i64 0, i64 %rs1
@@ -614,7 +592,6 @@ define i64 @zero1_setne_neg2048(i64 %a, i64 %rs1) {
; CHECK-LABEL: zero1_setne_neg2048:
; CHECK: # %bb.0:
; CHECK-NEXT: xori a0, a0, -2048
-; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vt.maskc a0, a1, a0
; CHECK-NEXT: ret
%rc = icmp ne i64 %a, -2048
@@ -626,7 +603,6 @@ define i64 @zero2_setne_neg2048(i64 %a, i64 %rs1) {
; CHECK-LABEL: zero2_setne_neg2048:
; CHECK: # %bb.0:
; CHECK-NEXT: xori a0, a0, -2048
-; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vt.maskcn a0, a1, a0
; CHECK-NEXT: ret
%rc = icmp ne i64 %a, -2048
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