[PATCH] D141127: AMDGPU/GlobalISel: Widen s1 SGPR constants during regbankselect

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll:71
 ; WAVE64-NEXT:    s_waitcnt lgkmcnt(0)
-; WAVE64-NEXT:    s_xor_b32 s0, s0, -1
+; WAVE64-NEXT:    s_xor_b32 s0, s0, 1
 ; WAVE64-NEXT:    s_and_b32 s0, s0, 1
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Pierre-vh wrote:
> If I understand correctly, it was interpreted as 1 on all lanes before (so -1 as a 32 bit value) but now we're widening the constant so it's just 1, and the end result is the same?
The next instruction is an s_and_b32 1 to clear the high bits. We're missing simplify known bits anyway


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141127/new/

https://reviews.llvm.org/D141127