[llvm] b4d4432 - AMDGPU/GlobalISel: Add missing test for implicit_def regbankselect
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 6 05:58:16 PST 2023
Author: Matt Arsenault
Date: 2023-01-06T08:58:10-05:00
New Revision: b4d44322d9e840f4209c2791ec0414695790ac33
URL: https://github.com/llvm/llvm-project/commit/b4d44322d9e840f4209c2791ec0414695790ac33
DIFF: https://github.com/llvm/llvm-project/commit/b4d44322d9e840f4209c2791ec0414695790ac33.diff
LOG: AMDGPU/GlobalISel: Add missing test for implicit_def regbankselect
Added:
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
new file mode 100644
index 000000000000..acfe7fb3de9d
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
@@ -0,0 +1,205 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: test_implicit_def_s32_vgpr_use
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_implicit_def_s32_vgpr_use
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[DEF]](s32)
+ ; CHECK-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s32), addrspace 1)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_IMPLICIT_DEF
+ G_STORE %1, %0 :: (store (s32), addrspace 1)
+
+...
+
+---
+name: test_implicit_def_s32_sgpr_use
+legalized: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_implicit_def_s32_sgpr_use
+ ; CHECK: [[DEF:%[0-9]+]]:sgpr(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.sendmsg), 0, [[DEF]](s32)
+ %0:_(s32) = G_IMPLICIT_DEF
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.sendmsg), 0, %0
+
+...
+
+---
+name: test_implicit_def_s64_vgpr_use
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_implicit_def_s64_vgpr_use
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[DEF]](s64)
+ ; CHECK-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store (s64), addrspace 1)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_IMPLICIT_DEF
+ G_STORE %1, %0 :: (store (s64), addrspace 1)
+
+...
+
+---
+name: test_implicit_def_v3s32_vgpr_use
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_implicit_def_v3s32_vgpr_use
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(<3 x s32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<3 x s32>) = COPY [[DEF]](<3 x s32>)
+ ; CHECK-NEXT: G_STORE [[COPY1]](<3 x s32>), [[COPY]](p1) :: (store (<3 x s32>), align 4, addrspace 1)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(<3 x s32>) = G_IMPLICIT_DEF
+ G_STORE %1, %0 :: (store (<3 x s32>), addrspace 1, align 4)
+
+...
+
+---
+name: test_implicit_def_v4s32_vgpr_use
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_implicit_def_v4s32_vgpr_use
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(<4 x s32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[DEF]](<4 x s32>)
+ ; CHECK-NEXT: G_STORE [[COPY1]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 4, addrspace 1)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(<4 x s32>) = G_IMPLICIT_DEF
+ G_STORE %1, %0 :: (store (<4 x s32>), addrspace 1, align 4)
+
+...
+
+---
+name: test_implicit_def_s64_sgpr_use
+legalized: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_implicit_def_s64_sgpr_use
+ ; CHECK: [[DEF:%[0-9]+]]:sgpr(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[DEF]](s64)
+ %0:_(s64) = G_IMPLICIT_DEF
+ $sgpr8_sgpr9 = COPY %0
+
+...
+
+---
+name: test_implicit_def_s128_sgpr_use
+legalized: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_implicit_def_s128_sgpr_use
+ ; CHECK: [[DEF:%[0-9]+]]:sgpr(s128) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: $sgpr8_sgpr9_sgpr10_sgpr11 = COPY [[DEF]](s128)
+ %0:_(s128) = G_IMPLICIT_DEF
+ $sgpr8_sgpr9_sgpr10_sgpr11 = COPY %0
+
+...
+
+---
+name: test_implicit_def_s1_sgpr_use
+legalized: true
+body: |
+ bb.0:
+ liveins: $sgpr8, $sgpr9
+ ; CHECK-LABEL: name: test_implicit_def_s1_sgpr_use
+ ; CHECK: liveins: $sgpr8, $sgpr9
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr8
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr9
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s1) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[DEF]](s1)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[SELECT]](s32)
+ %0:_(s32) = COPY $sgpr8
+ %1:_(s32) = COPY $sgpr9
+ %2:_(s1) = G_IMPLICIT_DEF
+ %3:_(s32) = G_SELECT %2, %0, %1
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: test_implicit_def_s1_vcc_use
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: test_implicit_def_s1_vcc_use
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s1) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[DEF]](s1)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY2]](s1), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[SELECT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s1) = G_IMPLICIT_DEF
+ %3:_(s32) = G_SELECT %2, %0, %1
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: test_implicit_def_s1_explicit_vcc_use_0
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: test_implicit_def_s1_explicit_vcc_use_0
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s1) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[DEF]](s1)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY2]](s1), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[SELECT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:vcc(s1) = G_IMPLICIT_DEF
+ %3:_(s32) = G_SELECT %2, %0, %1
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+name: test_implicit_def_s1_explicit_vcc_use_1
+legalized: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_implicit_def_s1_explicit_vcc_use_1
+ ; CHECK: [[DEF:%[0-9]+]]:sgpr(s1) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY [[DEF]](s1)
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]](s1)
+ %2:vcc(s1) = G_IMPLICIT_DEF
+ S_ENDPGM 0, implicit %2
+
+...
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