[llvm] 6fe8593 - AMDGPU/GlobalISel: Add wave32 checks to bool test
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 6 05:58:15 PST 2023
Author: Matt Arsenault
Date: 2023-01-06T08:58:10-05:00
New Revision: 6fe85933d4df1b381ba0f00ede3354db2aa3f326
URL: https://github.com/llvm/llvm-project/commit/6fe85933d4df1b381ba0f00ede3354db2aa3f326
DIFF: https://github.com/llvm/llvm-project/commit/6fe85933d4df1b381ba0f00ede3354db2aa3f326.diff
LOG: AMDGPU/GlobalISel: Add wave32 checks to bool test
Added:
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
index 5227d74414792..7b3bc41a82593 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
@@ -1,15 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -march=amdgcn -mcpu=hawaii -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,WAVE64 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,WAVE32 %s
; End to end tests for scalar vs. vector boolean legalization strategies.
define amdgpu_ps float @select_vgpr_sgpr_trunc_cond(i32 inreg %a, i32 %b, i32 %c) {
-; GCN-LABEL: select_vgpr_sgpr_trunc_cond:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_and_b32 s0, 1, s0
-; GCN-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GCN-NEXT: ; return to shader part epilog
+; WAVE64-LABEL: select_vgpr_sgpr_trunc_cond:
+; WAVE64: ; %bb.0:
+; WAVE64-NEXT: s_and_b32 s0, 1, s0
+; WAVE64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
+; WAVE64-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; WAVE64-NEXT: ; return to shader part epilog
+;
+; WAVE32-LABEL: select_vgpr_sgpr_trunc_cond:
+; WAVE32: ; %bb.0:
+; WAVE32-NEXT: s_and_b32 s0, 1, s0
+; WAVE32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; WAVE32-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; WAVE32-NEXT: ; return to shader part epilog
%cc = trunc i32 %a to i1
%r = select i1 %cc, i32 %b, i32 %c
%r.f = bitcast i32 %r to float
@@ -17,13 +25,21 @@ define amdgpu_ps float @select_vgpr_sgpr_trunc_cond(i32 inreg %a, i32 %b, i32 %c
}
define amdgpu_ps float @select_vgpr_sgpr_trunc_and_cond(i32 inreg %a.0, i32 inreg %a.1, i32 %b, i32 %c) {
-; GCN-LABEL: select_vgpr_sgpr_trunc_and_cond:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_and_b32 s0, s0, s1
-; GCN-NEXT: s_and_b32 s0, 1, s0
-; GCN-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GCN-NEXT: ; return to shader part epilog
+; WAVE64-LABEL: select_vgpr_sgpr_trunc_and_cond:
+; WAVE64: ; %bb.0:
+; WAVE64-NEXT: s_and_b32 s0, s0, s1
+; WAVE64-NEXT: s_and_b32 s0, 1, s0
+; WAVE64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
+; WAVE64-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; WAVE64-NEXT: ; return to shader part epilog
+;
+; WAVE32-LABEL: select_vgpr_sgpr_trunc_and_cond:
+; WAVE32: ; %bb.0:
+; WAVE32-NEXT: s_and_b32 s0, s0, s1
+; WAVE32-NEXT: s_and_b32 s0, 1, s0
+; WAVE32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; WAVE32-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; WAVE32-NEXT: ; return to shader part epilog
%cc.0 = trunc i32 %a.0 to i1
%cc.1 = trunc i32 %a.1 to i1
%and = and i1 %cc.0, %cc.1
@@ -48,22 +64,39 @@ define amdgpu_ps i32 @select_sgpr_trunc_and_cond(i32 inreg %a.0, i32 inreg %a.1,
}
define amdgpu_kernel void @sgpr_trunc_brcond(i32 %cond) {
-; GCN-LABEL: sgpr_trunc_brcond:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_dword s0, s[0:1], 0x9
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_xor_b32 s0, s0, -1
-; GCN-NEXT: s_and_b32 s0, s0, 1
-; GCN-NEXT: s_cmp_lg_u32 s0, 0
-; GCN-NEXT: s_cbranch_scc1 .LBB3_2
-; GCN-NEXT: ; %bb.1: ; %bb0
-; GCN-NEXT: v_mov_b32_e32 v0, 0
-; GCN-NEXT: flat_store_dword v[0:1], v0
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: .LBB3_2: ; %bb1
-; GCN-NEXT: v_mov_b32_e32 v0, 1
-; GCN-NEXT: flat_store_dword v[0:1], v0
-; GCN-NEXT: s_waitcnt vmcnt(0)
+; WAVE64-LABEL: sgpr_trunc_brcond:
+; WAVE64: ; %bb.0: ; %entry
+; WAVE64-NEXT: s_load_dword s0, s[0:1], 0x24
+; WAVE64-NEXT: s_waitcnt lgkmcnt(0)
+; WAVE64-NEXT: s_xor_b32 s0, s0, -1
+; WAVE64-NEXT: s_and_b32 s0, s0, 1
+; WAVE64-NEXT: s_cmp_lg_u32 s0, 0
+; WAVE64-NEXT: s_cbranch_scc1 .LBB3_2
+; WAVE64-NEXT: ; %bb.1: ; %bb0
+; WAVE64-NEXT: v_mov_b32_e32 v0, 0
+; WAVE64-NEXT: global_store_dword v[0:1], v0, off
+; WAVE64-NEXT: s_waitcnt vmcnt(0)
+; WAVE64-NEXT: .LBB3_2: ; %bb1
+; WAVE64-NEXT: v_mov_b32_e32 v0, 1
+; WAVE64-NEXT: global_store_dword v[0:1], v0, off
+; WAVE64-NEXT: s_waitcnt vmcnt(0)
+;
+; WAVE32-LABEL: sgpr_trunc_brcond:
+; WAVE32: ; %bb.0: ; %entry
+; WAVE32-NEXT: s_load_dword s0, s[0:1], 0x24
+; WAVE32-NEXT: s_waitcnt lgkmcnt(0)
+; WAVE32-NEXT: s_xor_b32 s0, s0, -1
+; WAVE32-NEXT: s_and_b32 s0, s0, 1
+; WAVE32-NEXT: s_cmp_lg_u32 s0, 0
+; WAVE32-NEXT: s_cbranch_scc1 .LBB3_2
+; WAVE32-NEXT: ; %bb.1: ; %bb0
+; WAVE32-NEXT: v_mov_b32_e32 v0, 0
+; WAVE32-NEXT: global_store_dword v[0:1], v0, off
+; WAVE32-NEXT: s_waitcnt_vscnt null, 0x0
+; WAVE32-NEXT: .LBB3_2: ; %bb1
+; WAVE32-NEXT: v_mov_b32_e32 v0, 1
+; WAVE32-NEXT: global_store_dword v[0:1], v0, off
+; WAVE32-NEXT: s_waitcnt_vscnt null, 0x0
entry:
%trunc = trunc i32 %cond to i1
br i1 %trunc, label %bb0, label %bb1
@@ -78,23 +111,41 @@ bb1:
}
define amdgpu_kernel void @brcond_sgpr_trunc_and(i32 %cond0, i32 %cond1) {
-; GCN-LABEL: brcond_sgpr_trunc_and:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_and_b32 s0, s0, s1
-; GCN-NEXT: s_xor_b32 s0, s0, -1
-; GCN-NEXT: s_and_b32 s0, s0, 1
-; GCN-NEXT: s_cmp_lg_u32 s0, 0
-; GCN-NEXT: s_cbranch_scc1 .LBB4_2
-; GCN-NEXT: ; %bb.1: ; %bb0
-; GCN-NEXT: v_mov_b32_e32 v0, 0
-; GCN-NEXT: flat_store_dword v[0:1], v0
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: .LBB4_2: ; %bb1
-; GCN-NEXT: v_mov_b32_e32 v0, 1
-; GCN-NEXT: flat_store_dword v[0:1], v0
-; GCN-NEXT: s_waitcnt vmcnt(0)
+; WAVE64-LABEL: brcond_sgpr_trunc_and:
+; WAVE64: ; %bb.0: ; %entry
+; WAVE64-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; WAVE64-NEXT: s_waitcnt lgkmcnt(0)
+; WAVE64-NEXT: s_and_b32 s0, s0, s1
+; WAVE64-NEXT: s_xor_b32 s0, s0, -1
+; WAVE64-NEXT: s_and_b32 s0, s0, 1
+; WAVE64-NEXT: s_cmp_lg_u32 s0, 0
+; WAVE64-NEXT: s_cbranch_scc1 .LBB4_2
+; WAVE64-NEXT: ; %bb.1: ; %bb0
+; WAVE64-NEXT: v_mov_b32_e32 v0, 0
+; WAVE64-NEXT: global_store_dword v[0:1], v0, off
+; WAVE64-NEXT: s_waitcnt vmcnt(0)
+; WAVE64-NEXT: .LBB4_2: ; %bb1
+; WAVE64-NEXT: v_mov_b32_e32 v0, 1
+; WAVE64-NEXT: global_store_dword v[0:1], v0, off
+; WAVE64-NEXT: s_waitcnt vmcnt(0)
+;
+; WAVE32-LABEL: brcond_sgpr_trunc_and:
+; WAVE32: ; %bb.0: ; %entry
+; WAVE32-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; WAVE32-NEXT: s_waitcnt lgkmcnt(0)
+; WAVE32-NEXT: s_and_b32 s0, s0, s1
+; WAVE32-NEXT: s_xor_b32 s0, s0, -1
+; WAVE32-NEXT: s_and_b32 s0, s0, 1
+; WAVE32-NEXT: s_cmp_lg_u32 s0, 0
+; WAVE32-NEXT: s_cbranch_scc1 .LBB4_2
+; WAVE32-NEXT: ; %bb.1: ; %bb0
+; WAVE32-NEXT: v_mov_b32_e32 v0, 0
+; WAVE32-NEXT: global_store_dword v[0:1], v0, off
+; WAVE32-NEXT: s_waitcnt_vscnt null, 0x0
+; WAVE32-NEXT: .LBB4_2: ; %bb1
+; WAVE32-NEXT: v_mov_b32_e32 v0, 1
+; WAVE32-NEXT: global_store_dword v[0:1], v0, off
+; WAVE32-NEXT: s_waitcnt_vscnt null, 0x0
entry:
%trunc0 = trunc i32 %cond0 to i1
%trunc1 = trunc i32 %cond1 to i1
More information about the llvm-commits
mailing list