[llvm] 239a174 - [RISCV] Prevent constant hoisting for or/and/xor that can use bseti/bclri/binvi.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-01-05T11:18:31-08:00
New Revision: 239a174d92dd2bd99ecb1308dc8937040895b04d

URL: https://github.com/llvm/llvm-project/commit/239a174d92dd2bd99ecb1308dc8937040895b04d
DIFF: https://github.com/llvm/llvm-project/commit/239a174d92dd2bd99ecb1308dc8937040895b04d.diff

LOG: [RISCV] Prevent constant hoisting for or/and/xor that can use bseti/bclri/binvi.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D140928

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 39a2b740fa6f7..02ce1b135f7f2 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -124,13 +124,22 @@ InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
     // zext.w
     if (Imm == UINT64_C(0xffffffff) && ST->hasStdExtZba())
       return TTI::TCC_Free;
+    // bclri
+    if (ST->hasStdExtZbs() && (~Imm).isPowerOf2())
+      return TTI::TCC_Free;
     if (Inst && Idx == 1 && Imm.getBitWidth() <= ST->getXLen() &&
         canUseShiftPair(Inst, Imm))
       return TTI::TCC_Free;
-    [[fallthrough]];
+    Takes12BitImm = true;
+    break;
   case Instruction::Add:
+    Takes12BitImm = true;
+    break;
   case Instruction::Or:
   case Instruction::Xor:
+    // bseti/binvi
+    if (ST->hasStdExtZbs() && Imm.isPowerOf2())
+      return TTI::TCC_Free;
     Takes12BitImm = true;
     break;
   case Instruction::Mul:

diff  --git a/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll b/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
index 7ee53f4cbc852..97aa19e68f917 100644
--- a/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
+++ b/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
@@ -95,3 +95,30 @@ define i32 @test10(i32 %a, i32 %b) nounwind {
   %5 = mul i32 %2, %4
   ret i32 %5
 }
+
+; bseti
+define i64 @test11(i64 %a) nounwind "target-features"="+zbs" {
+; CHECK-LABEL: test11
+; CHECK: or i64 %a, 8589934592
+  %1 = or i64 %a, 8589934592 ; 1 << 33
+  %2 = or i64 %1, 8589934592 ; 1 << 33
+  ret i64 %2
+}
+
+; binvi
+define i64 @test12(i64 %a) nounwind "target-features"="+zbs" {
+; CHECK-LABEL: test12
+; CHECK: xor i64 %a, -9223372036854775808
+  %1 = xor i64 %a, -9223372036854775808 ; 1 << 63
+  %2 = xor i64 %1, -9223372036854775808 ; 1 << 63
+  ret i64 %2
+}
+
+; bclri
+define i64 @test13(i64 %a) nounwind "target-features"="+zbs" {
+; CHECK-LABEL: test13
+; CHECK: and i64 %a, -281474976710657
+  %1 = and i64 %a, -281474976710657 ; ~(1 << 48)
+  %2 = and i64 %1, -281474976710657 ; ~(1 << 48)
+  ret i64 %2
+}