[llvm] 90cf22b - [InstCombine][NFC] Regenerate test cases by update_test_checks.py
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 4 22:27:50 PST 2023
Author: luxufan
Date: 2023-01-05T14:22:07+08:00
New Revision: 90cf22b91b30ffc12aeee3db4e8e996dedb61c83
URL: https://github.com/llvm/llvm-project/commit/90cf22b91b30ffc12aeee3db4e8e996dedb61c83
DIFF: https://github.com/llvm/llvm-project/commit/90cf22b91b30ffc12aeee3db4e8e996dedb61c83.diff
LOG: [InstCombine][NFC] Regenerate test cases by update_test_checks.py
Added:
Modified:
llvm/test/Transforms/InstCombine/overflow-mul.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/overflow-mul.ll b/llvm/test/Transforms/InstCombine/overflow-mul.ll
index ba379710635b6..cc1c79fa032d6 100644
--- a/llvm/test/Transforms/InstCombine/overflow-mul.ll
+++ b/llvm/test/Transforms/InstCombine/overflow-mul.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -passes=instcombine < %s | FileCheck %s
; The last test needs this weird datalayout.
@@ -14,14 +15,17 @@ target datalayout = "i32:8:8"
; return mul(zext x, zext y) > MAX
define i32 @pr4917_1(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: @pr4917_1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[UMUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i32, i1 } [[UMUL]], 1
+; CHECK-NEXT: [[RETVAL:%.*]] = zext i1 [[OVERFLOW]] to i32
+; CHECK-NEXT: ret i32 [[RETVAL]]
+;
entry:
%l = zext i32 %x to i64
%r = zext i32 %y to i64
-; CHECK-NOT: zext i32
%mul64 = mul i64 %l, %r
-; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
%overflow = icmp ugt i64 %mul64, 4294967295
-; CHECK: extractvalue { i32, i1 } [[MUL]], 1
%retval = zext i1 %overflow to i32
ret i32 %retval
}
@@ -29,14 +33,17 @@ entry:
; return mul(zext x, zext y) >= MAX+1
define i32 @pr4917_1a(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: @pr4917_1a(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[UMUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i32, i1 } [[UMUL]], 1
+; CHECK-NEXT: [[RETVAL:%.*]] = zext i1 [[OVERFLOW]] to i32
+; CHECK-NEXT: ret i32 [[RETVAL]]
+;
entry:
%l = zext i32 %x to i64
%r = zext i32 %y to i64
-; CHECK-NOT: zext i32
%mul64 = mul i64 %l, %r
-; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
%overflow = icmp uge i64 %mul64, 4294967296
-; CHECK: extractvalue { i32, i1 } [[MUL]], 1
%retval = zext i1 %overflow to i32
ret i32 %retval
}
@@ -45,18 +52,20 @@ entry:
; mul(x, y) is used
define i32 @pr4917_2(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: @pr4917_2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[UMUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT: [[UMUL_VALUE:%.*]] = extractvalue { i32, i1 } [[UMUL]], 0
+; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i32, i1 } [[UMUL]], 1
+; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[OVERFLOW]], i32 [[UMUL_VALUE]], i32 111
+; CHECK-NEXT: ret i32 [[RETVAL]]
+;
entry:
%l = zext i32 %x to i64
%r = zext i32 %y to i64
-; CHECK-NOT: zext i32
%mul64 = mul i64 %l, %r
-; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
%overflow = icmp ugt i64 %mul64, 4294967295
-; CHECK-DAG: [[VAL:%.*]] = extractvalue { i32, i1 } [[MUL]], 0
%mul32 = trunc i64 %mul64 to i32
-; CHECK-DAG: [[OVFL:%.*]] = extractvalue { i32, i1 } [[MUL]], 1
%retval = select i1 %overflow, i32 %mul32, i32 111
-; CHECK: select i1 [[OVFL]], i32 [[VAL]]
ret i32 %retval
}
@@ -64,11 +73,18 @@ entry:
; mul is used in non-truncate
define i64 @pr4917_3(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: @pr4917_3(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[L:%.*]] = zext i32 [[X:%.*]] to i64
+; CHECK-NEXT: [[R:%.*]] = zext i32 [[Y:%.*]] to i64
+; CHECK-NEXT: [[MUL64:%.*]] = mul nuw i64 [[L]], [[R]]
+; CHECK-NEXT: [[OVERFLOW:%.*]] = icmp ugt i64 [[MUL64]], 4294967295
+; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[OVERFLOW]], i64 [[MUL64]], i64 111
+; CHECK-NEXT: ret i64 [[RETVAL]]
+;
entry:
%l = zext i32 %x to i64
%r = zext i32 %y to i64
%mul64 = mul i64 %l, %r
-; CHECK-NOT: umul.with.overflow.i32
%overflow = icmp ugt i64 %mul64, 4294967295
%retval = select i1 %overflow, i64 %mul64, i64 111
ret i64 %retval
@@ -77,15 +93,18 @@ entry:
; return mul(zext x, zext y) <= MAX
define i32 @pr4917_4(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: @pr4917_4(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[UMUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT: [[TMP0:%.*]] = extractvalue { i32, i1 } [[UMUL]], 1
+; CHECK-NEXT: [[OVERFLOW:%.*]] = xor i1 [[TMP0]], true
+; CHECK-NEXT: [[RETVAL:%.*]] = zext i1 [[OVERFLOW]] to i32
+; CHECK-NEXT: ret i32 [[RETVAL]]
+;
entry:
%l = zext i32 %x to i64
%r = zext i32 %y to i64
-; CHECK-NOT: zext i32
%mul64 = mul i64 %l, %r
-; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
%overflow = icmp ule i64 %mul64, 4294967295
-; CHECK: extractvalue { i32, i1 } [[MUL]], 1
-; CHECK: xor
%retval = zext i1 %overflow to i32
ret i32 %retval
}
@@ -93,15 +112,18 @@ entry:
; return mul(zext x, zext y) < MAX+1
define i32 @pr4917_4a(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: @pr4917_4a(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[UMUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT: [[TMP0:%.*]] = extractvalue { i32, i1 } [[UMUL]], 1
+; CHECK-NEXT: [[OVERFLOW:%.*]] = xor i1 [[TMP0]], true
+; CHECK-NEXT: [[RETVAL:%.*]] = zext i1 [[OVERFLOW]] to i32
+; CHECK-NEXT: ret i32 [[RETVAL]]
+;
entry:
%l = zext i32 %x to i64
%r = zext i32 %y to i64
-; CHECK-NOT: zext i32
%mul64 = mul i64 %l, %r
-; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
%overflow = icmp ult i64 %mul64, 4294967296
-; CHECK: extractvalue { i32, i1 } [[MUL]], 1
-; CHECK: xor
%retval = zext i1 %overflow to i32
ret i32 %retval
}
@@ -109,33 +131,40 @@ entry:
; operands of mul are of
diff erent size
define i32 @pr4917_5(i32 %x, i8 %y) nounwind {
; CHECK-LABEL: @pr4917_5(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[Y:%.*]] to i32
+; CHECK-NEXT: [[UMUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[X:%.*]], i32 [[TMP0]])
+; CHECK-NEXT: [[UMUL_VALUE:%.*]] = extractvalue { i32, i1 } [[UMUL]], 0
+; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i32, i1 } [[UMUL]], 1
+; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[OVERFLOW]], i32 [[UMUL_VALUE]], i32 111
+; CHECK-NEXT: ret i32 [[RETVAL]]
+;
entry:
%l = zext i32 %x to i64
%r = zext i8 %y to i64
-; CHECK: [[Y:%.*]] = zext i8 %y to i32
%mul64 = mul i64 %l, %r
%overflow = icmp ugt i64 %mul64, 4294967295
%mul32 = trunc i64 %mul64 to i32
-; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 [[Y]])
-; CHECK-DAG: [[VAL:%.*]] = extractvalue { i32, i1 } [[MUL]], 0
-; CHECK-DAG: [[OVFL:%.*]] = extractvalue { i32, i1 } [[MUL]], 1
%retval = select i1 %overflow, i32 %mul32, i32 111
-; CHECK: select i1 [[OVFL]], i32 [[VAL]]
ret i32 %retval
}
; mul(zext x, zext y) != zext trunc mul
define i32 @pr4918_1(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: @pr4918_1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[UMUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT: [[TMP0:%.*]] = extractvalue { i32, i1 } [[UMUL]], 1
+; CHECK-NEXT: [[RETVAL:%.*]] = zext i1 [[TMP0]] to i32
+; CHECK-NEXT: ret i32 [[RETVAL]]
+;
entry:
%l = zext i32 %x to i64
%r = zext i32 %y to i64
%mul64 = mul i64 %l, %r
-; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
%part32 = trunc i64 %mul64 to i32
%part64 = zext i32 %part32 to i64
%overflow = icmp ne i64 %mul64, %part64
-; CHECK: [[OVFL:%.*]] = extractvalue { i32, i1 } [[MUL:%.*]], 1
%retval = zext i1 %overflow to i32
ret i32 %retval
}
@@ -143,40 +172,53 @@ entry:
; mul(zext x, zext y) == zext trunc mul
define i32 @pr4918_2(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: @pr4918_2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[UMUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT: [[TMP0:%.*]] = extractvalue { i32, i1 } [[UMUL]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = xor i1 [[TMP0]], true
+; CHECK-NEXT: [[RETVAL:%.*]] = zext i1 [[TMP1]] to i32
+; CHECK-NEXT: ret i32 [[RETVAL]]
+;
entry:
%l = zext i32 %x to i64
%r = zext i32 %y to i64
%mul64 = mul i64 %l, %r
-; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
%part32 = trunc i64 %mul64 to i32
%part64 = zext i32 %part32 to i64
%overflow = icmp eq i64 %mul64, %part64
-; CHECK: extractvalue { i32, i1 } [[MUL]]
%retval = zext i1 %overflow to i32
-; CHECK: xor
ret i32 %retval
}
; zext trunc mul != mul(zext x, zext y)
define i32 @pr4918_3(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: @pr4918_3(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[UMUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT: [[TMP0:%.*]] = extractvalue { i32, i1 } [[UMUL]], 1
+; CHECK-NEXT: [[RETVAL:%.*]] = zext i1 [[TMP0]] to i32
+; CHECK-NEXT: ret i32 [[RETVAL]]
+;
entry:
%l = zext i32 %x to i64
%r = zext i32 %y to i64
%mul64 = mul i64 %l, %r
-; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
%part32 = trunc i64 %mul64 to i32
%part64 = zext i32 %part32 to i64
%overflow = icmp ne i64 %part64, %mul64
-; CHECK: extractvalue { i32, i1 } [[MUL]], 1
%retval = zext i1 %overflow to i32
ret i32 %retval
}
define <4 x i32> @pr20113(<4 x i16> %a, <4 x i16> %b) {
-; CHECK-LABEL: @pr20113
-; CHECK-NOT: mul.with.overflow
-; CHECK: ret
+; CHECK-LABEL: @pr20113(
+; CHECK-NEXT: [[VMOVL_I_I726:%.*]] = zext <4 x i16> [[A:%.*]] to <4 x i32>
+; CHECK-NEXT: [[VMOVL_I_I712:%.*]] = zext <4 x i16> [[B:%.*]] to <4 x i32>
+; CHECK-NEXT: [[MUL_I703:%.*]] = mul nuw <4 x i32> [[VMOVL_I_I712]], [[VMOVL_I_I726]]
+; CHECK-NEXT: [[MUL_I703_LOBIT:%.*]] = ashr <4 x i32> [[MUL_I703]], <i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT: [[MUL_I703_LOBIT_NOT:%.*]] = xor <4 x i32> [[MUL_I703_LOBIT]], <i32 -1, i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT: ret <4 x i32> [[MUL_I703_LOBIT_NOT]]
+;
%vmovl.i.i726 = zext <4 x i16> %a to <4 x i32>
%vmovl.i.i712 = zext <4 x i16> %b to <4 x i32>
%mul.i703 = mul <4 x i32> %vmovl.i.i712, %vmovl.i.i726
@@ -189,9 +231,10 @@ define <4 x i32> @pr20113(<4 x i16> %a, <4 x i16> %b) {
@pr21445_data = external global i32
define i1 @pr21445(i8 %a) {
; CHECK-LABEL: @pr21445(
-; CHECK-NEXT: %[[umul:.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %a, i8 ptrtoint (ptr @pr21445_data to i8))
-; CHECK-NEXT: %[[cmp:.*]] = extractvalue { i8, i1 } %[[umul]], 1
-; CHECK-NEXT: ret i1 %[[cmp]]
+; CHECK-NEXT: [[UMUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[A:%.*]], i8 ptrtoint (ptr @pr21445_data to i8))
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i8, i1 } [[UMUL]], 1
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
%ext = zext i8 %a to i32
%mul = mul i32 %ext, zext (i8 ptrtoint (ptr @pr21445_data to i8) to i32)
%and = and i32 %mul, 255
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