[llvm] c43a787 - [InstCombine] don't let 'exact' inhibit demanded bits folds for udiv

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2023-01-04T13:13:02-05:00
New Revision: c43a7874a3012ae0c6aa983a882a0b23284c2ec7

URL: https://github.com/llvm/llvm-project/commit/c43a7874a3012ae0c6aa983a882a0b23284c2ec7
DIFF: https://github.com/llvm/llvm-project/commit/c43a7874a3012ae0c6aa983a882a0b23284c2ec7.diff

LOG: [InstCombine] don't let 'exact' inhibit demanded bits folds for udiv

We shouldn't penalize instructions that have extra flags.

Drop the poison-generating flags if needed instead of bailing out.
This makes canonicalization/optimization more uniform.

There is a chance that dropping flags will cause some
other transform to not fire, but we added a preliminary
patch to avoid that with:
f0faea571403

See D140665 for more details.

Added: 
    

Modified: 
    llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
    llvm/test/Transforms/InstCombine/udiv-simplify.ll

Removed: 
    


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diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index 5fa5cc57f18e4..77d6754229662 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -796,18 +796,18 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
     // UDiv doesn't demand low bits that are zero in the divisor.
     const APInt *SA;
     if (match(I->getOperand(1), m_APInt(SA))) {
-      // If the shift is exact, then it does demand the low bits.
-      if (cast<UDivOperator>(I)->isExact())
-        break;
-
-      // FIXME: Take the demanded mask of the result into account.
+      // TODO: Take the demanded mask of the result into account.
       unsigned RHSTrailingZeros = SA->countTrailingZeros();
       APInt DemandedMaskIn =
           APInt::getHighBitsSet(BitWidth, BitWidth - RHSTrailingZeros);
-      if (SimplifyDemandedBits(I, 0, DemandedMaskIn, LHSKnown, Depth + 1))
+      if (SimplifyDemandedBits(I, 0, DemandedMaskIn, LHSKnown, Depth + 1)) {
+        // We can't guarantee that "exact" is still true after changing the
+        // the dividend.
+        I->dropPoisonGeneratingFlags();
         return I;
+      }
 
-      // Propagate zero bits from the input.
+      // Increase high zero bits from the input.
       Known.Zero.setHighBits(std::min(
           BitWidth, LHSKnown.Zero.countLeadingOnes() + RHSTrailingZeros));
     } else {

diff  --git a/llvm/test/Transforms/InstCombine/udiv-simplify.ll b/llvm/test/Transforms/InstCombine/udiv-simplify.ll
index f33c744ca79d6..6971b6c915b58 100644
--- a/llvm/test/Transforms/InstCombine/udiv-simplify.ll
+++ b/llvm/test/Transforms/InstCombine/udiv-simplify.ll
@@ -117,13 +117,11 @@ define i8 @udiv_demanded_high_bits_set(i8 %x, i8 %y) {
   ret i8 %r
 }
 
-; TODO: This should fold the same as above.
+; This should fold the same as above.
 
 define i8 @udiv_exact_demanded_high_bits_set(i8 %x, i8 %y) {
 ; CHECK-LABEL: @udiv_exact_demanded_high_bits_set(
-; CHECK-NEXT:    [[O:%.*]] = or i8 [[X:%.*]], -4
-; CHECK-NEXT:    [[R:%.*]] = udiv exact i8 [[O]], 12
-; CHECK-NEXT:    ret i8 [[R]]
+; CHECK-NEXT:    ret i8 21
 ;
   %o = or i8 %x, -4
   %r = udiv exact i8 %o, 12
@@ -142,12 +140,11 @@ define i8 @udiv_demanded_low_bits_clear(i8 %a) {
   ret i8 %u
 }
 
-; TODO: This should fold the same as above.
+; This should fold the same as above.
 
 define i8 @udiv_exact_demanded_low_bits_clear(i8 %a) {
 ; CHECK-LABEL: @udiv_exact_demanded_low_bits_clear(
-; CHECK-NEXT:    [[O:%.*]] = and i8 [[A:%.*]], -4
-; CHECK-NEXT:    [[U:%.*]] = udiv exact i8 [[O]], 12
+; CHECK-NEXT:    [[U:%.*]] = udiv i8 [[A:%.*]], 12
 ; CHECK-NEXT:    ret i8 [[U]]
 ;
   %o = and i8 %a, -4