[PATCH] D140928: [RISCV] Prevent constant hoisting for or/and/xor that can use bseti/bclri/binvi.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 3 15:34:52 PST 2023
craig.topper created this revision.
craig.topper added reviewers: reames, asb, kito-cheng.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson.
Herald added a reviewer: ributzka.
Herald added a project: All.
craig.topper requested review of this revision.
Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D140928
Files:
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
Index: llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
===================================================================
--- llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
+++ llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
@@ -95,3 +95,30 @@
%5 = mul i32 %2, %4
ret i32 %5
}
+
+; bseti
+define i64 @test11(i64 %a) nounwind "target-features"="+zbs" {
+; CHECK-LABEL: test11
+; CHECK: or i64 %a, 8589934592
+ %1 = or i64 %a, 8589934592 ; 1 << 33
+ %2 = or i64 %1, 8589934592 ; 1 << 33
+ ret i64 %2
+}
+
+; binvi
+define i64 @test12(i64 %a) nounwind "target-features"="+zbs" {
+; CHECK-LABEL: test12
+; CHECK: xor i64 %a, -9223372036854775808
+ %1 = xor i64 %a, -9223372036854775808 ; 1 << 63
+ %2 = xor i64 %1, -9223372036854775808 ; 1 << 63
+ ret i64 %2
+}
+
+; bclri
+define i64 @test13(i64 %a) nounwind "target-features"="+zbs" {
+; CHECK-LABEL: test13
+; CHECK: and i64 %a, -281474976710657
+ %1 = and i64 %a, -281474976710657 ; ~(1 << 48)
+ %2 = and i64 %1, -281474976710657 ; ~(1 << 48)
+ ret i64 %2
+}
Index: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -124,13 +124,22 @@
// zext.w
if (Imm == UINT64_C(0xffffffff) && ST->hasStdExtZba())
return TTI::TCC_Free;
+ // bclri
+ if (ST->hasStdExtZbs() && (~Imm).isPowerOf2())
+ return TTI::TCC_Free;
if (Inst && Idx == 1 && Imm.getBitWidth() <= ST->getXLen() &&
canUseShiftPair(Inst, Imm))
return TTI::TCC_Free;
- [[fallthrough]];
+ Takes12BitImm = true;
+ break;
case Instruction::Add:
+ Takes12BitImm = true;
+ break;
case Instruction::Or:
case Instruction::Xor:
+ // bseti/binvi
+ if (ST->hasStdExtZbs() && Imm.isPowerOf2())
+ return TTI::TCC_Free;
Takes12BitImm = true;
break;
case Instruction::Mul:
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D140928.486107.patch
Type: text/x-patch
Size: 1987 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230103/d6ebf962/attachment.bin>
More information about the llvm-commits
mailing list