[PATCH] D140569: [AVR] Custom lower 32-bit shift instructions

[Ben Shi via Phabricator via llvm-commits]

benshi001 added a comment.

Beside my latest two pieces of inline comment, There is failure of `LLVM.CodeGen/AVR::shift.ll` in the `pre-merge checks` on both windows and linux, I think you need to have a check.



================
Comment at: llvm/lib/Target/AVR/AVRISelLowering.cpp:1844
+
+  bool ShiftLeft = Opc == ISD::SHL;
+  bool ArithmeticShift = Opc == ISD::SRA;
----------------
can it be `const bool ShiftLeft = Opc == ISD::SHL;` ?


================
Comment at: llvm/lib/Target/AVR/AVRISelLowering.cpp:1870
+    // Shift one to the right.
+    for (size_t i = 0; i < Regs.size(); i++) {
+      Register Out = MRI.createVirtualRegister(&AVR::GPR8RegClass);
----------------
This loop variable need to be `I`, like the above loop.


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https://reviews.llvm.org/D140569