[llvm] 9f40d9f - [AMDGPU][MC][GFX11] Correct encoding of neg modifier for v_dot2_f32_bf16

[Dmitry Preobrazhensky via llvm-commits]

Author: Dmitry Preobrazhensky
Date: 2022-12-30T16:25:22+03:00
New Revision: 9f40d9ffd18685f1605869efb358f4532112c295

URL: https://github.com/llvm/llvm-project/commit/9f40d9ffd18685f1605869efb358f4532112c295
DIFF: https://github.com/llvm/llvm-project/commit/9f40d9ffd18685f1605869efb358f4532112c295.diff

LOG: [AMDGPU][MC][GFX11] Correct encoding of neg modifier for v_dot2_f32_bf16

Fix a bug with neg_lo:[0,1,0] and neg_hi:[0,1,0] modifiers - they are accepted but not encoded.

Differential Revision: https://reviews.llvm.org/D140470

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/VOP3PInstructions.td
    llvm/test/MC/AMDGPU/gfx11_asm_vop3p.s
    llvm/test/MC/AMDGPU/gfx11_asm_vop3p_features.s
    llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p.txt

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index 78c4455fc9848..e33ba7acd03a3 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -359,10 +359,14 @@ defm V_DOT8_I32_I4  : VOP3PInst<"v_dot8_i32_i4",
 
 } // End SubtargetPredicate = HasDot1Insts
 
+def DOT2_BF16_Profile
+  : VOP3P_Profile<VOP_F32_V2I16_V2I16_F32, VOP3_REGULAR, /*HasDPP*/ 1> {
+  let HasSrc1Mods = 1;
+}
+
 let SubtargetPredicate = HasDot8Insts  in {
 
-defm V_DOT2_F32_BF16 : VOP3PInst<"v_dot2_f32_bf16",
-  VOP3P_Profile<VOP_F32_V2I16_V2I16_F32, VOP3_REGULAR, /*HasDPP*/ 1>,
+defm V_DOT2_F32_BF16 : VOP3PInst<"v_dot2_f32_bf16", DOT2_BF16_Profile,
   int_amdgcn_fdot2_f32_bf16, 1>;
 
 } // End SubtargetPredicate = HasDot8Insts

diff  --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3p.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3p.s
index 7a703dfc48fd6..4426ec4bbbeb5 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3p.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3p.s
@@ -42,8 +42,8 @@ v_dot2_f32_bf16 v5, -1, m0, 0xaf123456
 v_dot2_f32_bf16 v5, src_scc, vcc_lo, src_scc neg_lo:[1,0,0] neg_hi:[1,0,0]
 // GFX11: [0x05,0x41,0x1a,0xcc,0xfd,0xd4,0xf4,0x3b]
 
-v_dot2_f32_bf16 v255, 0xfe0b, vcc_hi, 0.5 neg_lo:[0,0,0] neg_hi:[0,0,0] clamp
-// GFX11: [0xff,0xc0,0x1a,0xcc,0xff,0xd6,0xc0,0x1b,0x0b,0xfe,0x00,0x00]
+v_dot2_f32_bf16 v255, 0xfe0b, vcc_hi, 0.5 neg_lo:[0,1,0] neg_hi:[0,1,0] clamp
+// GFX11: [0xff,0xc2,0x1a,0xcc,0xff,0xd6,0xc0,0x5b,0x0b,0xfe,0x00,0x00]
 
 v_dot2_f32_f16 v5, v1, v2, s3
 // GFX11: [0x05,0x40,0x13,0xcc,0x01,0x05,0x0e,0x18]

diff  --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_features.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_features.s
index b1458c5100d88..3c89a6468b3b2 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_features.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_features.s
@@ -140,4 +140,4 @@ v_dot2_f32_bf16 v0, v1, v2, v3
 // GFX11: v_dot2_f32_bf16 v0, v1, v2, v3          ; encoding: [0x00,0x40,0x1a,0xcc,0x01,0x05,0x0e,0x1c]
 
 v_dot2_f32_bf16 v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1]
-// GFX11: v_dot2_f32_bf16 v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1] ; encoding: [0x00,0x45,0x1a,0xcc,0x01,0x05,0x0e,0x3c]
+// GFX11: v_dot2_f32_bf16 v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1] ; encoding: [0x00,0x45,0x1a,0xcc,0x01,0x05,0x0e,0x7c]

diff  --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p.txt
index 41a8abb5628c4..9f146b8818c44 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p.txt
@@ -46,6 +46,9 @@
 # GFX11: v_dot2_f32_bf16 v255, 0xfe0b, vcc_hi, 0.5 neg_lo:[1,0,0] neg_hi:[1,0,0] clamp ; encoding: [0xff,0xc1,0x1a,0xcc,0xff,0xd6,0xc0,0x3b,0x0b,0xfe,0x00,0x00]
 0xff,0xc1,0x1a,0xcc,0xff,0xd6,0xc0,0x3b,0x0b,0xfe,0x00,0x00
 
+# GFX11: v_dot2_f32_bf16 v255, 0xfe0b, vcc_hi, 0.5 neg_lo:[0,1,0] neg_hi:[0,1,0] clamp ; encoding: [0xff,0xc2,0x1a,0xcc,0xff,0xd6,0xc0,0x5b,0x0b,0xfe,0x00,0x00]
+0xff,0xc2,0x1a,0xcc,0xff,0xd6,0xc0,0x5b,0x0b,0xfe,0x00,0x00
+
 # GFX11: v_dot2_f32_f16 v5, v1, v2, s3           ; encoding: [0x05,0x40,0x13,0xcc,0x01,0x05,0x0e,0x18]
 0x05,0x40,0x13,0xcc,0x01,0x05,0x0e,0x18