[PATCH] D138837: [ScheduleDAG] Support REQ_SEQUENCE unscheduling

[Filipp Zhinkin via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG98265db84c33: [ScheduleDAG] Support REQ_SEQUENCE unscheduling (authored by fzhinkin).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138837/new/

https://reviews.llvm.org/D138837

Files:
  llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
  llvm/test/CodeGen/ARM/unschedule-reg-sequence.ll


Index: llvm/test/CodeGen/ARM/unschedule-reg-sequence.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/ARM/unschedule-reg-sequence.ll
@@ -0,0 +1,21 @@
+; RUN: llc -verify-machineinstrs < %s
+; Regression test for https://github.com/llvm/llvm-project/issues/58911
+
+target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "armv7-none-unknown-eabi"
+
+ at a = dso_local global i64 0, align 8
+ at d = dso_local local_unnamed_addr global i32 0, align 4
+
+define dso_local void @f() nounwind {
+entry:
+  store volatile i64 0, ptr @a, align 8
+  %0 = load i32, ptr @d, align 4
+  %tobool.not = icmp eq i32 %0, 0
+  %conv = zext i32 %0 to i64
+  %sub = sub nsw i64 0, %conv
+  %cond = select i1 %tobool.not, i64 0, i64 %sub
+  store volatile i64 %cond, ptr @a, align 8
+  ret void
+}
+
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -302,6 +302,8 @@
 
 }  // end anonymous namespace
 
+static constexpr unsigned RegSequenceCost = 1;
+
 /// GetCostForDef - Looks up the register class and cost for a given definition.
 /// Typically this just means looking up the representative register class,
 /// but for untyped values (MVT::Untyped) it means inspecting the node's
@@ -333,7 +335,7 @@
       unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
       const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
       RegClass = RC->getID();
-      Cost = 1;
+      Cost = RegSequenceCost;
       return;
     }
 
@@ -2302,6 +2304,16 @@
       RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
       continue;
     }
+    if (POpc == TargetOpcode::REG_SEQUENCE) {
+      unsigned DstRCIdx =
+          cast<ConstantSDNode>(PN->getOperand(0))->getZExtValue();
+      const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
+      unsigned RCId = RC->getID();
+      // REG_SEQUENCE is untyped, so getRepRegClassCostFor could not be used
+      // here. Instead use the same constant as in GetCostForDef.
+      RegPressure[RCId] += RegSequenceCost;
+      continue;
+    }
     unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
     for (unsigned i = 0; i != NumDefs; ++i) {
       MVT VT = PN->getSimpleValueType(i);


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D138837.485684.patch
Type: text/x-patch
Size: 2449 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221230/b17ad2e9/attachment.bin>