[llvm] bd9c0f0 - [RISCV] Add Svpbmt extension support.
Yeting Kuo via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 28 23:57:59 PST 2022
Author: Yeting Kuo
Date: 2022-12-28T23:57:54-08:00
New Revision: bd9c0f082b20d96ced1e5f5ddc1506afffc0f8d3
URL: https://github.com/llvm/llvm-project/commit/bd9c0f082b20d96ced1e5f5ddc1506afffc0f8d3
DIFF: https://github.com/llvm/llvm-project/commit/bd9c0f082b20d96ced1e5f5ddc1506afffc0f8d3.diff
LOG: [RISCV] Add Svpbmt extension support.
Spec of Svpbmt: https://github.com/riscv/riscv-isa-manual/blob/master/src/supervisor.tex#L2399
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D140692
Added:
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/TargetParser/RISCVISAInfo.cpp
llvm/test/CodeGen/RISCV/attributes.ll
Removed:
################################################################################
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 7791703cbbe46..c514ad889d0b2 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -41,6 +41,7 @@
// CHECK-NOT: __riscv_zicbom
// CHECK-NOT: __riscv_zicboz
// CHECK-NOT: __riscv_svnapot
+// CHECK-NOT: __riscv_svpbmt
// CHECK-NOT: __riscv_svinval
// CHECK-NOT: __riscv_xventanacondops
// CHECK-NOT: __riscv_zcd
@@ -436,6 +437,12 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SVNAPOT-EXT %s
// CHECK-SVNAPOT-EXT: __riscv_svnapot 1000000{{$}}
+// RUN: %clang -target riscv32 -march=rv32isvpbmt -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SVPBMT-EXT %s
+// RUN: %clang -target riscv64 -march=rv64isvpbmt -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SVPBMT-EXT %s
+// CHECK-SVPBMT-EXT: __riscv_svpbmt 1000000{{$}}
+
// RUN: %clang -target riscv32 -march=rv32isvinval -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SVINVAL-EXT %s
// RUN: %clang -target riscv64 -march=rv64isvinval -x c -E -dM %s \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 522988f8b053d..70e86ed6a30c8 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -53,6 +53,7 @@ on support follow.
``F`` Supported
``M`` Supported
``Svinval`` Assembly Support
+ ``Svpbmt`` Supported
``V`` Supported
``Zba`` Supported
``Zbb`` Supported
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index c94d426fb72e3..eb851a7e1ed92 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -413,6 +413,10 @@ def FeatureStdExtSvnapot
: SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
"'Svnapot' (NAPOT Translation Contiguity)">;
+def FeatureStdExtSvpbmt
+ : SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
+ "'Svpbmt' (Page-Based Memory Types)">;
+
def FeatureStdExtSvinval
: SubtargetFeature<"svinval", "HasStdExtSvinval", "true",
"'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 328749b12845c..4f56d1aa00955 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -103,6 +103,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"zicbop", RISCVExtensionVersion{1, 0}},
{"svnapot", RISCVExtensionVersion{1, 0}},
+ {"svpbmt", RISCVExtensionVersion{1, 0}},
{"svinval", RISCVExtensionVersion{1, 0}},
{"xventanacondops", RISCVExtensionVersion{1, 0}},
{"xtheadvdot", RISCVExtensionVersion{1, 0}},
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index dda8d65350658..4acb1ad2fc3bb 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -37,6 +37,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV32ZICBOZ %s
; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s
; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV32SVNAPOT %s
+; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefix=RV32SVPBMT %s
; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV32ZCA %s
@@ -77,6 +78,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
+; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck --check-prefix=RV64SVPBMT %s
; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefix=RV64XVENTANACONDOPS %s
; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefix=RV64XTHEADVDOT %s
@@ -121,6 +123,7 @@
; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
+; RV32SVPBMT: .attribute 5, "rv32i2p0_svpbmt1p0"
; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
; RV32ZCA: .attribute 5, "rv32i2p0_zca0p70"
@@ -162,6 +165,7 @@
; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
+; RV64SVPBMT: .attribute 5, "rv64i2p0_svpbmt1p0"
; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
; RV64XTHEADVDOT: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
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