[PATCH] D140674: [RISCV] Prefer ADDI over ORI if the known bits are disjoint.

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG79d6e9c7130c: [RISCV] Prefer ADDI over ORI if the known bits are disjoint. (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140674/new/

https://reviews.llvm.org/D140674

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/or-is-add.ll
  llvm/test/CodeGen/RISCV/rv64zba.ll
  llvm/test/CodeGen/RISCV/vararg.ll

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