[llvm] 6357b63 - [RISCV] Add RISCV::XORI to RISCVDAGToDAGISel::hasAllNBitUsers.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 28 15:33:50 PST 2022
Author: Craig Topper
Date: 2022-12-28T15:17:41-08:00
New Revision: 6357b6373525f2c6154500727cc55bda2ee6910f
URL: https://github.com/llvm/llvm-project/commit/6357b6373525f2c6154500727cc55bda2ee6910f
DIFF: https://github.com/llvm/llvm-project/commit/6357b6373525f2c6154500727cc55bda2ee6910f.diff
LOG: [RISCV] Add RISCV::XORI to RISCVDAGToDAGISel::hasAllNBitUsers.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/test/CodeGen/RISCV/select-constant-xor.ll
llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index e80200bf05e5..3898dbbfaf85 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2368,6 +2368,7 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
case RISCV::AND:
case RISCV::OR:
case RISCV::XOR:
+ case RISCV::XORI:
case RISCV::ANDN:
case RISCV::ORN:
case RISCV::XNOR:
diff --git a/llvm/test/CodeGen/RISCV/select-constant-xor.ll b/llvm/test/CodeGen/RISCV/select-constant-xor.ll
index 02e6dd4b1bdc..2e26ae78e2dd 100644
--- a/llvm/test/CodeGen/RISCV/select-constant-xor.ll
+++ b/llvm/test/CodeGen/RISCV/select-constant-xor.ll
@@ -225,7 +225,7 @@ define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
; RV64-LABEL: oneusecmp:
; RV64: # %bb.0:
; RV64-NEXT: sext.w a3, a0
-; RV64-NEXT: srli a0, a3, 31
+; RV64-NEXT: sraiw a0, a0, 31
; RV64-NEXT: xori a0, a0, 127
; RV64-NEXT: bltz a3, .LBB10_2
; RV64-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll b/llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
index 6cc02a81accb..075e6f9dfd3b 100644
--- a/llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
+++ b/llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
@@ -1631,7 +1631,7 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: slli a6, a6, 3
; RV64I-NEXT: slli t2, t2, 35
; RV64I-NEXT: or a6, t2, a6
-; RV64I-NEXT: addi t1, a6, -128
+; RV64I-NEXT: addiw t1, a6, -128
; RV64I-NEXT: addi t2, a6, -192
; RV64I-NEXT: slli t0, a3, 1
; RV64I-NEXT: bltz t2, .LBB9_2
@@ -1671,7 +1671,7 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: .LBB9_9:
; RV64I-NEXT: sll t3, a3, t6
; RV64I-NEXT: srli t4, a4, 1
-; RV64I-NEXT: sub t6, t5, a6
+; RV64I-NEXT: subw t6, t5, a6
; RV64I-NEXT: xori t6, t6, 63
; RV64I-NEXT: srl t4, t4, t6
; RV64I-NEXT: or t4, t3, t4
@@ -2507,7 +2507,7 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: slli a6, a6, 3
; RV64I-NEXT: slli t2, t2, 35
; RV64I-NEXT: or a6, t2, a6
-; RV64I-NEXT: addi t1, a6, -128
+; RV64I-NEXT: addiw t1, a6, -128
; RV64I-NEXT: addi t2, a6, -192
; RV64I-NEXT: srli t0, a3, 1
; RV64I-NEXT: bltz t2, .LBB10_2
@@ -2547,7 +2547,7 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: .LBB10_9:
; RV64I-NEXT: srl t3, a3, t6
; RV64I-NEXT: slli t4, a4, 1
-; RV64I-NEXT: sub t6, t5, a6
+; RV64I-NEXT: subw t6, t5, a6
; RV64I-NEXT: xori t6, t6, 63
; RV64I-NEXT: sll t4, t4, t6
; RV64I-NEXT: or t4, t3, t4
@@ -3388,7 +3388,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: slli a4, a4, 3
; RV64I-NEXT: slli t3, t3, 35
; RV64I-NEXT: or a4, t3, a4
-; RV64I-NEXT: addi t3, a4, -128
+; RV64I-NEXT: addiw t3, a4, -128
; RV64I-NEXT: addi t4, a4, -192
; RV64I-NEXT: slli t0, a3, 1
; RV64I-NEXT: bltz t4, .LBB11_2
@@ -3444,7 +3444,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: .LBB11_13:
; RV64I-NEXT: sll t5, a3, s0
; RV64I-NEXT: srli t6, a5, 1
-; RV64I-NEXT: sub s0, t1, a4
+; RV64I-NEXT: subw s0, t1, a4
; RV64I-NEXT: xori s0, s0, 63
; RV64I-NEXT: srl t6, t6, s0
; RV64I-NEXT: or t5, t5, t6
diff --git a/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll b/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
index 5ae623057375..90af50f2ac1a 100644
--- a/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
+++ b/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
@@ -1603,7 +1603,7 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: or a6, a6, t1
; RV64I-NEXT: slli a6, a6, 32
; RV64I-NEXT: or a6, a6, t2
-; RV64I-NEXT: addi t1, a6, -128
+; RV64I-NEXT: addiw t1, a6, -128
; RV64I-NEXT: addi t2, a6, -192
; RV64I-NEXT: slli t0, a3, 1
; RV64I-NEXT: bltz t2, .LBB9_2
@@ -1643,7 +1643,7 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: .LBB9_9:
; RV64I-NEXT: sll t3, a3, t6
; RV64I-NEXT: srli t4, a4, 1
-; RV64I-NEXT: sub t6, t5, a6
+; RV64I-NEXT: subw t6, t5, a6
; RV64I-NEXT: xori t6, t6, 63
; RV64I-NEXT: srl t4, t4, t6
; RV64I-NEXT: or t4, t3, t4
@@ -2476,7 +2476,7 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: or a6, a6, t1
; RV64I-NEXT: slli a6, a6, 32
; RV64I-NEXT: or a6, a6, t2
-; RV64I-NEXT: addi t1, a6, -128
+; RV64I-NEXT: addiw t1, a6, -128
; RV64I-NEXT: addi t2, a6, -192
; RV64I-NEXT: srli t0, a3, 1
; RV64I-NEXT: bltz t2, .LBB10_2
@@ -2516,7 +2516,7 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: .LBB10_9:
; RV64I-NEXT: srl t3, a3, t6
; RV64I-NEXT: slli t4, a4, 1
-; RV64I-NEXT: sub t6, t5, a6
+; RV64I-NEXT: subw t6, t5, a6
; RV64I-NEXT: xori t6, t6, 63
; RV64I-NEXT: sll t4, t4, t6
; RV64I-NEXT: or t4, t3, t4
@@ -3354,7 +3354,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: or a4, a4, t2
; RV64I-NEXT: slli a4, a4, 32
; RV64I-NEXT: or a4, a4, t3
-; RV64I-NEXT: addi t3, a4, -128
+; RV64I-NEXT: addiw t3, a4, -128
; RV64I-NEXT: addi t4, a4, -192
; RV64I-NEXT: slli t0, a3, 1
; RV64I-NEXT: bltz t4, .LBB11_2
@@ -3410,7 +3410,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {
; RV64I-NEXT: .LBB11_13:
; RV64I-NEXT: sll t5, a3, s0
; RV64I-NEXT: srli t6, a5, 1
-; RV64I-NEXT: sub s0, t1, a4
+; RV64I-NEXT: subw s0, t1, a4
; RV64I-NEXT: xori s0, s0, 63
; RV64I-NEXT: srl t6, t6, s0
; RV64I-NEXT: or t5, t5, t6
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