[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:97
   bool HasRV32 = false;
+  bool HasStdExtZvkb = false;
+  bool HasStdExtZvkg = false;
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This needs to be rebased, it's all autogenerated by tablegen now.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138807/new/

https://reviews.llvm.org/D138807