[llvm] 1184ede - [RISCV] Add const qualifiers to some function arguments. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-12-28T11:20:17-08:00
New Revision: 1184ede46f45c8d003207e7c436f45e910bf50a3

URL: https://github.com/llvm/llvm-project/commit/1184ede46f45c8d003207e7c436f45e910bf50a3
DIFF: https://github.com/llvm/llvm-project/commit/1184ede46f45c8d003207e7c436f45e910bf50a3.diff

LOG: [RISCV] Add const qualifiers to some function arguments. NFC

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfo.h
    llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 75da8ab2184db..9eaef3cd37397 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2607,7 +2607,8 @@ bool RISCV::hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2) {
 // Checks if all users only demand the lower word of the original instruction's
 // result.
 // TODO: handle multiple interdependent transformations
-bool RISCV::hasAllWUsers(const MachineInstr &OrigMI, MachineRegisterInfo &MRI) {
+bool RISCV::hasAllWUsers(const MachineInstr &OrigMI,
+                         const MachineRegisterInfo &MRI) {
 
   SmallPtrSet<const MachineInstr *, 4> Visited;
   SmallVector<const MachineInstr *, 4> Worklist;

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 60d0282119469..e03582efc6521 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -252,7 +252,7 @@ static constexpr int64_t VLMaxSentinel = -1LL;
 
 // Returns true if all uses of OrigMI only depend on the lower word of its
 // output, so we can transform OrigMI to the corresponding W-version.
-bool hasAllWUsers(const MachineInstr &MI, MachineRegisterInfo &MRI);
+bool hasAllWUsers(const MachineInstr &MI, const MachineRegisterInfo &MRI);
 } // namespace RISCV
 
 namespace RISCVVPseudosTable {

diff  --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
index a6f74f3ba1b45..061b4defef1cf 100644
--- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -62,7 +62,8 @@ FunctionPass *llvm::createRISCVSExtWRemovalPass() {
 
 // This function returns true if the machine instruction always outputs a value
 // where bits 63:32 match bit 31.
-static bool isSignExtendingOpW(MachineInstr &MI, MachineRegisterInfo &MRI) {
+static bool isSignExtendingOpW(const MachineInstr &MI,
+                               const MachineRegisterInfo &MRI) {
   uint64_t TSFlags = MI.getDesc().TSFlags;
 
   // Instructions that can be determined from opcode are marked in tablegen.
@@ -93,7 +94,7 @@ static bool isSignExtendingOpW(MachineInstr &MI, MachineRegisterInfo &MRI) {
   return false;
 }
 
-static bool isSignExtendedW(Register SrcReg, MachineRegisterInfo &MRI,
+static bool isSignExtendedW(Register SrcReg, const MachineRegisterInfo &MRI,
                             SmallPtrSetImpl<MachineInstr *> &FixableDef) {
 
   SmallPtrSet<const MachineInstr *, 4> Visited;
@@ -342,7 +343,8 @@ bool RISCVSExtWRemoval::runOnMachineFunction(MachineFunction &MF) {
       // If all users only use the lower bits, this sext.w is redundant.
       // Or if all definitions reaching MI sign-extend their output,
       // then sext.w is redundant.
-      if (!RISCV::hasAllWUsers(*MI, MRI) && !isSignExtendedW(SrcReg, MRI, FixableDefs))
+      if (!RISCV::hasAllWUsers(*MI, MRI) &&
+          !isSignExtendedW(SrcReg, MRI, FixableDefs))
         continue;
 
       Register DstReg = MI->getOperand(0).getReg();