[llvm] 00926c3 - [RISCV] Fix typos in RISCVUsage.rst

[Kito Cheng via llvm-commits]

Author: Jie Fu
Date: 2022-12-28T16:33:41+08:00
New Revision: 00926c30be083dae76d04c209751d03102bd7fed

URL: https://github.com/llvm/llvm-project/commit/00926c30be083dae76d04c209751d03102bd7fed
DIFF: https://github.com/llvm/llvm-project/commit/00926c30be083dae76d04c209751d03102bd7fed.diff

LOG: [RISCV] Fix typos in RISCVUsage.rst

Fix typos `riscv-toolchai-convention` --> `riscv-toolchain-convention`

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D140717

Added: 
    

Modified: 
    llvm/docs/RISCVUsage.rst

Removed: 
    


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diff  --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index c5f947a76eb28..522988f8b053d 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -158,10 +158,10 @@ It is our intention to follow the naming conventions described in `riscv-non-isa
 The current vendor extensions supported are:
 
 ``XVentanaCondOps``
-  LLVM implements `version 1.0.0 of the VTx-family custom instructions specification <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf>`_ by Ventana Micro Systems.  All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchai-convention document linked above.  These instructions are only available for riscv64 at this time.
+  LLVM implements `version 1.0.0 of the VTx-family custom instructions specification <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf>`_ by Ventana Micro Systems.  All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above.  These instructions are only available for riscv64 at this time.
 
 ``XTHeadVdot``
-  LLVM implements `version 1.0.0 of the THeadV-family custom instructions specification <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.0/xthead-2022-12-04-2.2.0.pdf>`_ by T-HEAD of Alibaba.  All instructions are prefixed with `th.` as described in the specification, and the riscv-toolchai-convention document linked above.
+  LLVM implements `version 1.0.0 of the THeadV-family custom instructions specification <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.0/xthead-2022-12-04-2.2.0.pdf>`_ by T-HEAD of Alibaba.  All instructions are prefixed with `th.` as described in the specification, and the riscv-toolchain-convention document linked above.
 
 
 Specification Documents