[llvm] 0ad57bf - [PowerPC] Enable track-subreg-liveness by default
Qiu Chaofan via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 27 22:09:44 PST 2022
Author: Qiu Chaofan
Date: 2022-12-28T14:09:29+08:00
New Revision: 0ad57bf236df9be06811e52c85d4a8ff5f89d387
URL: https://github.com/llvm/llvm-project/commit/0ad57bf236df9be06811e52c85d4a8ff5f89d387
DIFF: https://github.com/llvm/llvm-project/commit/0ad57bf236df9be06811e52c85d4a8ff5f89d387.diff
LOG: [PowerPC] Enable track-subreg-liveness by default
This option helps some MMA related cases to reduce unnecessary copies.
Reviewed By: shchenz
Differential Revision: https://reviews.llvm.org/D108902
Added:
Modified:
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/test/CodeGen/PowerPC/all-atomics.ll
llvm/test/CodeGen/PowerPC/crbits.ll
llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
llvm/test/CodeGen/PowerPC/mma-acc-copy-hints.ll
llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll
llvm/test/CodeGen/PowerPC/p10-spill-creq.ll
llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll
llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
llvm/test/CodeGen/PowerPC/pr45709.ll
llvm/test/CodeGen/PowerPC/spe.ll
llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
index 08993690dbc3d..fb37bf4b3362f 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -37,8 +37,10 @@ using namespace llvm;
#define GET_SUBTARGETINFO_CTOR
#include "PPCGenSubtargetInfo.inc"
-static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
-cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
+static cl::opt<bool>
+ UseSubRegLiveness("ppc-track-subreg-liveness",
+ cl::desc("Enable subregister liveness tracking for PPC"),
+ cl::init(true), cl::Hidden);
static cl::opt<bool>
EnableMachinePipeliner("ppc-enable-pipeliner",
diff --git a/llvm/test/CodeGen/PowerPC/all-atomics.ll b/llvm/test/CodeGen/PowerPC/all-atomics.ll
index 0ab8ab5ee0007..528d68f6a1b24 100644
--- a/llvm/test/CodeGen/PowerPC/all-atomics.ll
+++ b/llvm/test/CodeGen/PowerPC/all-atomics.ll
@@ -3070,9 +3070,9 @@ define dso_local void @test_op_and_fetch() local_unnamed_addr #0 {
; CHECK-NEXT: bne 0, .LBB2_81
; CHECK-NEXT: # %bb.82: # %entry
; CHECK-NEXT: lwsync
+; CHECK-NEXT: lbz 20, uc at toc@l(3)
; CHECK-NEXT: nand 25, 21, 25
; CHECK-NEXT: li 21, -1
-; CHECK-NEXT: lbz 20, uc at toc@l(3)
; CHECK-NEXT: std 21, 8(23)
; CHECK-NEXT: std 25, u128 at toc@l(24)
; CHECK-NEXT: addis 25, 2, s128 at toc@ha
diff --git a/llvm/test/CodeGen/PowerPC/crbits.ll b/llvm/test/CodeGen/PowerPC/crbits.ll
index 9105d332d21b0..61916e6101017 100644
--- a/llvm/test/CodeGen/PowerPC/crbits.ll
+++ b/llvm/test/CodeGen/PowerPC/crbits.ll
@@ -20,9 +20,9 @@ define zeroext i1 @test1(float %v1, float %v2) #0 {
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: fcmpu 5, 2, 2
; CHECK-NEXT: fcmpu 1, 2, 0
-; CHECK-NEXT: crnor 24, 3, 0
-; CHECK-NEXT: crnor 20, 23, 5
-; CHECK-NEXT: crnand 20, 24, 20
+; CHECK-NEXT: crnor 20, 3, 0
+; CHECK-NEXT: crnor 21, 23, 5
+; CHECK-NEXT: crnand 20, 20, 21
; CHECK-NEXT: isel 3, 0, 3, 20
; CHECK-NEXT: blr
;
@@ -33,9 +33,9 @@ define zeroext i1 @test1(float %v1, float %v2) #0 {
; CHECK-NO-ISEL-NEXT: li 3, 1
; CHECK-NO-ISEL-NEXT: fcmpu 5, 2, 2
; CHECK-NO-ISEL-NEXT: fcmpu 1, 2, 0
-; CHECK-NO-ISEL-NEXT: crnor 24, 3, 0
-; CHECK-NO-ISEL-NEXT: crnor 20, 23, 5
-; CHECK-NO-ISEL-NEXT: crnand 20, 24, 20
+; CHECK-NO-ISEL-NEXT: crnor 20, 3, 0
+; CHECK-NO-ISEL-NEXT: crnor 21, 23, 5
+; CHECK-NO-ISEL-NEXT: crnand 20, 20, 21
; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB0_1
; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL-NEXT: .LBB0_1: # %entry
@@ -71,9 +71,9 @@ define zeroext i1 @test2(float %v1, float %v2) #0 {
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: fcmpu 5, 2, 2
; CHECK-NEXT: fcmpu 1, 2, 0
-; CHECK-NEXT: crnor 24, 3, 0
-; CHECK-NEXT: crnor 20, 23, 5
-; CHECK-NEXT: creqv 20, 24, 20
+; CHECK-NEXT: crnor 20, 3, 0
+; CHECK-NEXT: crnor 21, 23, 5
+; CHECK-NEXT: creqv 20, 20, 21
; CHECK-NEXT: isel 3, 0, 3, 20
; CHECK-NEXT: blr
;
@@ -84,9 +84,9 @@ define zeroext i1 @test2(float %v1, float %v2) #0 {
; CHECK-NO-ISEL-NEXT: li 3, 1
; CHECK-NO-ISEL-NEXT: fcmpu 5, 2, 2
; CHECK-NO-ISEL-NEXT: fcmpu 1, 2, 0
-; CHECK-NO-ISEL-NEXT: crnor 24, 3, 0
-; CHECK-NO-ISEL-NEXT: crnor 20, 23, 5
-; CHECK-NO-ISEL-NEXT: creqv 20, 24, 20
+; CHECK-NO-ISEL-NEXT: crnor 20, 3, 0
+; CHECK-NO-ISEL-NEXT: crnor 21, 23, 5
+; CHECK-NO-ISEL-NEXT: creqv 20, 20, 21
; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB1_1
; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL-NEXT: .LBB1_1: # %entry
@@ -123,9 +123,9 @@ define zeroext i1 @test3(float %v1, float %v2, i32 signext %x) #0 {
; CHECK-NEXT: fcmpu 5, 1, 2
; CHECK-NEXT: fcmpu 1, 2, 0
; CHECK-NEXT: crnor 20, 23, 20
-; CHECK-NEXT: crnor 24, 3, 5
+; CHECK-NEXT: crnor 21, 3, 5
; CHECK-NEXT: cmpwi 5, -2
-; CHECK-NEXT: crandc 21, 24, 2
+; CHECK-NEXT: crandc 21, 21, 2
; CHECK-NEXT: creqv 20, 20, 21
; CHECK-NEXT: isel 3, 0, 3, 20
; CHECK-NEXT: blr
@@ -138,9 +138,9 @@ define zeroext i1 @test3(float %v1, float %v2, i32 signext %x) #0 {
; CHECK-NO-ISEL-NEXT: fcmpu 5, 1, 2
; CHECK-NO-ISEL-NEXT: fcmpu 1, 2, 0
; CHECK-NO-ISEL-NEXT: crnor 20, 23, 20
-; CHECK-NO-ISEL-NEXT: crnor 24, 3, 5
+; CHECK-NO-ISEL-NEXT: crnor 21, 3, 5
; CHECK-NO-ISEL-NEXT: cmpwi 5, -2
-; CHECK-NO-ISEL-NEXT: crandc 21, 24, 2
+; CHECK-NO-ISEL-NEXT: crandc 21, 21, 2
; CHECK-NO-ISEL-NEXT: creqv 20, 20, 21
; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB2_1
; CHECK-NO-ISEL-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
index 9d0d38a2b268c..6aae299786cc7 100644
--- a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
@@ -249,8 +249,8 @@ define i32 @test_f64_oge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-NEXT: efdcmpeq cr0, r6, r6
; SPE-NEXT: efdcmpeq cr1, r5, r5
; SPE-NEXT: efdcmplt cr5, r5, r6
-; SPE-NEXT: crand 4*cr6+lt, 4*cr1+gt, gt
-; SPE-NEXT: crandc 4*cr5+lt, 4*cr6+lt, 4*cr5+gt
+; SPE-NEXT: crand 4*cr5+lt, 4*cr1+gt, gt
+; SPE-NEXT: crandc 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
; SPE-NEXT: bclr 12, 4*cr5+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
@@ -283,8 +283,8 @@ define i32 @test_f64_ole_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-NEXT: efdcmpeq cr0, r6, r6
; SPE-NEXT: efdcmpeq cr1, r5, r5
; SPE-NEXT: efdcmpgt cr5, r5, r6
-; SPE-NEXT: crand 4*cr6+lt, 4*cr1+gt, gt
-; SPE-NEXT: crandc 4*cr5+lt, 4*cr6+lt, 4*cr5+gt
+; SPE-NEXT: crand 4*cr5+lt, 4*cr1+gt, gt
+; SPE-NEXT: crandc 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
; SPE-NEXT: bclr 12, 4*cr5+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
@@ -354,8 +354,8 @@ define i32 @test_f64_ugt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-NEXT: efdcmpeq cr0, r5, r5
; SPE-NEXT: efdcmpeq cr1, r7, r7
; SPE-NEXT: efdcmpgt cr5, r5, r7
-; SPE-NEXT: crnand 4*cr6+lt, 4*cr1+gt, gt
-; SPE-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr6+lt
+; SPE-NEXT: crnand 4*cr5+lt, 4*cr1+gt, gt
+; SPE-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; SPE-NEXT: bclr 12, 4*cr5+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
@@ -389,8 +389,8 @@ define i32 @test_f64_ult_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-NEXT: efdcmpeq cr0, r5, r5
; SPE-NEXT: efdcmpeq cr1, r7, r7
; SPE-NEXT: efdcmplt cr5, r5, r7
-; SPE-NEXT: crnand 4*cr6+lt, 4*cr1+gt, gt
-; SPE-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr6+lt
+; SPE-NEXT: crnand 4*cr5+lt, 4*cr1+gt, gt
+; SPE-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; SPE-NEXT: bclr 12, 4*cr5+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
diff --git a/llvm/test/CodeGen/PowerPC/mma-acc-copy-hints.ll b/llvm/test/CodeGen/PowerPC/mma-acc-copy-hints.ll
index 1a5edd80c825b..6b188d7c210e3 100644
--- a/llvm/test/CodeGen/PowerPC/mma-acc-copy-hints.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-acc-copy-hints.ll
@@ -26,18 +26,14 @@ define void @testMultiply(ptr nocapture noundef readonly %a, ptr nocapture nound
; CHECK-NEXT: std r29, -24(r30) # 8-byte Folded Spill
; CHECK-NEXT: mr r29, r5
; CHECK-NEXT: bl _Z15buildVectorPairPu13__vector_pairDv16_hS0_ at notoc
-; CHECK-NEXT: xxsetaccz acc1
-; CHECK-NEXT: xvf32gerpp acc1, v31, v30
+; CHECK-NEXT: xxsetaccz acc0
+; CHECK-NEXT: xvf32gerpp acc0, v31, v30
; CHECK-NEXT: lxv v3, 32(r1)
; CHECK-NEXT: lxv v2, 48(r1)
-; CHECK-NEXT: xvf32gerpp acc1, v3, v2
-; CHECK-NEXT: xxmfacc acc1
-; CHECK-NEXT: xxlor vs0, vs4, vs4
-; CHECK-NEXT: xxlor vs1, vs5, vs5
-; CHECK-NEXT: xxlor vs2, vs6, vs6
-; CHECK-NEXT: xxlor vs3, vs7, vs7
+; CHECK-NEXT: xvf32gerpp acc0, v3, v2
; CHECK-NEXT: lxv v31, -48(r30) # 16-byte Folded Reload
; CHECK-NEXT: lxv v30, -64(r30) # 16-byte Folded Reload
+; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs3, 0(r29)
; CHECK-NEXT: pstxv vs2, 8(r29), 0
; CHECK-NEXT: stxv vs1, 16(r29)
@@ -74,13 +70,13 @@ define void @testMultiply(ptr nocapture noundef readonly %a, ptr nocapture nound
; CHECK-BE-NEXT: lxv v3, 144(r1)
; CHECK-BE-NEXT: lxv v2, 128(r1)
; CHECK-BE-NEXT: xvf32gerpp acc1, v2, v3
+; CHECK-BE-NEXT: lxv v31, -48(r30) # 16-byte Folded Reload
+; CHECK-BE-NEXT: lxv v30, -64(r30) # 16-byte Folded Reload
; CHECK-BE-NEXT: xxmfacc acc1
; CHECK-BE-NEXT: xxlor vs1, vs6, vs6
; CHECK-BE-NEXT: xxlor vs0, vs7, vs7
; CHECK-BE-NEXT: xxlor vs3, vs4, vs4
; CHECK-BE-NEXT: xxlor vs2, vs5, vs5
-; CHECK-BE-NEXT: lxv v31, -48(r30) # 16-byte Folded Reload
-; CHECK-BE-NEXT: lxv v30, -64(r30) # 16-byte Folded Reload
; CHECK-BE-NEXT: stxv vs0, 0(r29)
; CHECK-BE-NEXT: pstxv vs1, 8(r29), 0
; CHECK-BE-NEXT: stxv vs2, 16(r29)
diff --git a/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll b/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
index ddfadd79deda5..f2b6c64934312 100644
--- a/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
@@ -377,8 +377,8 @@ define dso_local void @testLdStPair(i64 %SrcIdx, i64 %DstIdx) {
; LE-PAIRED: # %bb.0: # %entry
; LE-PAIRED-NEXT: plxv v3, g at PCREL+32(0), 1
; LE-PAIRED-NEXT: plxv v2, g at PCREL+48(0), 1
-; LE-PAIRED-NEXT: pstxv v3, g at PCREL+64(0), 1
; LE-PAIRED-NEXT: pstxv v2, g at PCREL+80(0), 1
+; LE-PAIRED-NEXT: pstxv v3, g at PCREL+64(0), 1
; LE-PAIRED-NEXT: blr
;
; BE-PAIRED-LABEL: testLdStPair:
@@ -544,8 +544,8 @@ define dso_local void @testUnalignedLdStPair() {
; LE-PAIRED: # %bb.0: # %entry
; LE-PAIRED-NEXT: plxv v3, g at PCREL+11(0), 1
; LE-PAIRED-NEXT: plxv v2, g at PCREL+27(0), 1
-; LE-PAIRED-NEXT: pstxv v3, g at PCREL+19(0), 1
; LE-PAIRED-NEXT: pstxv v2, g at PCREL+35(0), 1
+; LE-PAIRED-NEXT: pstxv v3, g at PCREL+19(0), 1
; LE-PAIRED-NEXT: blr
;
; BE-PAIRED-LABEL: testUnalignedLdStPair:
diff --git a/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll b/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
index 3e96e692e0525..8d03594fe1bfd 100644
--- a/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
@@ -31,10 +31,10 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
; CHECK-NEXT: stxv v31, 144(r1) # 16-byte Folded Spill
; CHECK-NEXT: vmr v31, v5
; CHECK-NEXT: vmr v30, v4
-; CHECK-NEXT: std r30, 160(r1) # 8-byte Folded Spill
; CHECK-NEXT: xxlor vs1, v29, v29
; CHECK-NEXT: xxlor vs2, v30, v30
; CHECK-NEXT: xxlor vs3, v31, v31
+; CHECK-NEXT: std r30, 160(r1) # 8-byte Folded Spill
; CHECK-NEXT: ld r30, 272(r1)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvf16ger2pp acc0, v2, v4
@@ -82,10 +82,10 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
; CHECK-BE-NEXT: stxv v31, 224(r1) # 16-byte Folded Spill
; CHECK-BE-NEXT: vmr v31, v5
; CHECK-BE-NEXT: vmr v30, v4
-; CHECK-BE-NEXT: std r30, 240(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: xxlor vs1, v29, v29
; CHECK-BE-NEXT: xxlor vs2, v30, v30
; CHECK-BE-NEXT: xxlor vs3, v31, v31
+; CHECK-BE-NEXT: std r30, 240(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: ld r30, 368(r1)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: xvf16ger2pp acc0, v2, v4
diff --git a/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll b/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
index ac1f9f5472d31..92d67bafd5183 100644
--- a/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
@@ -11,11 +11,10 @@ declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <
define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
; CHECK-LABEL: ass_acc:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmr v3, v2
-; CHECK-NEXT: xxlor vs0, v2, v2
-; CHECK-NEXT: xxlor vs1, v3, v3
+; CHECK-NEXT: xxlor vs3, v2, v2
; CHECK-NEXT: xxlor vs2, v2, v2
-; CHECK-NEXT: xxlor vs3, v3, v3
+; CHECK-NEXT: xxlor vs0, vs2, vs2
+; CHECK-NEXT: xxlor vs1, vs3, vs3
; CHECK-NEXT: stxv vs0, 48(r3)
; CHECK-NEXT: stxv vs1, 32(r3)
; CHECK-NEXT: stxv vs2, 16(r3)
@@ -24,11 +23,10 @@ define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
;
; CHECK-BE-LABEL: ass_acc:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vmr v3, v2
-; CHECK-BE-NEXT: xxlor vs0, v2, v2
-; CHECK-BE-NEXT: xxlor vs1, v3, v3
+; CHECK-BE-NEXT: xxlor vs3, v2, v2
; CHECK-BE-NEXT: xxlor vs2, v2, v2
-; CHECK-BE-NEXT: xxlor vs3, v3, v3
+; CHECK-BE-NEXT: xxlor vs0, vs2, vs2
+; CHECK-BE-NEXT: xxlor vs1, vs3, vs3
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs3, 48(r3)
@@ -45,11 +43,10 @@ declare <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1>)
define void @int_xxmtacc(ptr %ptr, <16 x i8> %vc) {
; CHECK-LABEL: int_xxmtacc:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmr v3, v2
-; CHECK-NEXT: xxlor vs0, v2, v2
-; CHECK-NEXT: xxlor vs1, v3, v3
+; CHECK-NEXT: xxlor vs3, v2, v2
; CHECK-NEXT: xxlor vs2, v2, v2
-; CHECK-NEXT: xxlor vs3, v3, v3
+; CHECK-NEXT: xxlor vs0, vs2, vs2
+; CHECK-NEXT: xxlor vs1, vs3, vs3
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: stxv vs0, 48(r3)
; CHECK-NEXT: stxv vs1, 32(r3)
@@ -59,11 +56,10 @@ define void @int_xxmtacc(ptr %ptr, <16 x i8> %vc) {
;
; CHECK-BE-LABEL: int_xxmtacc:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vmr v3, v2
-; CHECK-BE-NEXT: xxlor vs0, v2, v2
-; CHECK-BE-NEXT: xxlor vs1, v3, v3
+; CHECK-BE-NEXT: xxlor vs3, v2, v2
; CHECK-BE-NEXT: xxlor vs2, v2, v2
-; CHECK-BE-NEXT: xxlor vs3, v3, v3
+; CHECK-BE-NEXT: xxlor vs0, vs2, vs2
+; CHECK-BE-NEXT: xxlor vs1, vs3, vs3
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
@@ -84,11 +80,10 @@ declare <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1>)
define void @int_xxmfacc(ptr %ptr, <16 x i8> %vc) {
; CHECK-LABEL: int_xxmfacc:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmr v3, v2
-; CHECK-NEXT: xxlor vs0, v2, v2
-; CHECK-NEXT: xxlor vs1, v3, v3
+; CHECK-NEXT: xxlor vs3, v2, v2
; CHECK-NEXT: xxlor vs2, v2, v2
-; CHECK-NEXT: xxlor vs3, v3, v3
+; CHECK-NEXT: xxlor vs0, vs2, vs2
+; CHECK-NEXT: xxlor vs1, vs3, vs3
; CHECK-NEXT: stxv vs0, 48(r3)
; CHECK-NEXT: stxv vs1, 32(r3)
; CHECK-NEXT: stxv vs2, 16(r3)
@@ -97,11 +92,10 @@ define void @int_xxmfacc(ptr %ptr, <16 x i8> %vc) {
;
; CHECK-BE-LABEL: int_xxmfacc:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vmr v3, v2
-; CHECK-BE-NEXT: xxlor vs0, v2, v2
-; CHECK-BE-NEXT: xxlor vs1, v3, v3
+; CHECK-BE-NEXT: xxlor vs3, v2, v2
; CHECK-BE-NEXT: xxlor vs2, v2, v2
-; CHECK-BE-NEXT: xxlor vs3, v3, v3
+; CHECK-BE-NEXT: xxlor vs0, vs2, vs2
+; CHECK-BE-NEXT: xxlor vs1, vs3, vs3
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs3, 48(r3)
diff --git a/llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll b/llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll
index be395b468a17c..5ca8c7b02cab4 100644
--- a/llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll
+++ b/llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll
@@ -30,8 +30,8 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
; CHECK-NEXT: stxv v30, 128(r1) # 16-byte Folded Spill
; CHECK-NEXT: stxv v31, 144(r1) # 16-byte Folded Spill
; CHECK-NEXT: vmr v31, v5
-; CHECK-NEXT: vmr v30, v4
; CHECK-NEXT: vmr v29, v3
+; CHECK-NEXT: vmr v30, v4
; CHECK-NEXT: vmr v28, v2
; CHECK-NEXT: std r30, 160(r1) # 8-byte Folded Spill
; CHECK-NEXT: ld r30, 272(r1)
@@ -77,8 +77,8 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
; CHECK-BE-NEXT: stxv v30, 208(r1) # 16-byte Folded Spill
; CHECK-BE-NEXT: stxv v31, 224(r1) # 16-byte Folded Spill
; CHECK-BE-NEXT: vmr v31, v5
-; CHECK-BE-NEXT: vmr v30, v4
; CHECK-BE-NEXT: vmr v29, v3
+; CHECK-BE-NEXT: vmr v30, v4
; CHECK-BE-NEXT: vmr v28, v2
; CHECK-BE-NEXT: std r30, 240(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: ld r30, 368(r1)
diff --git a/llvm/test/CodeGen/PowerPC/p10-spill-creq.ll b/llvm/test/CodeGen/PowerPC/p10-spill-creq.ll
index fc5ef88e33798..a3799daf35b34 100644
--- a/llvm/test/CodeGen/PowerPC/p10-spill-creq.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-spill-creq.ll
@@ -29,160 +29,119 @@ define dso_local double @P10_Spill_CR_EQ(ptr %arg) local_unnamed_addr #0 {
; CHECK-NEXT: ld r3, 0(r3)
; CHECK-NEXT: ld r4, 0(0)
; CHECK-NEXT: ld r5, 56(0)
-; CHECK-NEXT: cmpdi cr1, r3, 0
-; CHECK-NEXT: cmpdi cr4, r4, 0
-; CHECK-NEXT: cmpdi cr6, r5, 0
-; CHECK-NEXT: cmpldi r3, 0
-; CHECK-NEXT: beq cr0, .LBB0_3
+; CHECK-NEXT: cmpdi r3, 0
+; CHECK-NEXT: cmpdi cr1, r4, 0
+; CHECK-NEXT: cmpdi cr5, r5, 0
+; CHECK-NEXT: cmpldi cr6, r3, 0
+; CHECK-NEXT: beq cr6, .LBB0_3
; CHECK-NEXT: # %bb.1: # %bb10
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: bc 12, 4*cr4+eq, .LBB0_4
+; CHECK-NEXT: bc 12, 4*cr1+eq, .LBB0_4
; CHECK-NEXT: .LBB0_2: # %bb14
; CHECK-NEXT: lwz r5, 0(r3)
; CHECK-NEXT: b .LBB0_5
; CHECK-NEXT: .LBB0_3:
; CHECK-NEXT: # implicit-def: $r3
-; CHECK-NEXT: bc 4, 4*cr4+eq, .LBB0_2
+; CHECK-NEXT: bc 4, 4*cr1+eq, .LBB0_2
; CHECK-NEXT: .LBB0_4:
; CHECK-NEXT: # implicit-def: $r5
; CHECK-NEXT: .LBB0_5: # %bb16
-; CHECK-NEXT: mfocrf r4, 64
-; CHECK-NEXT: crnot 4*cr2+un, 4*cr1+eq
-; CHECK-NEXT: crnot 4*cr5+lt, 4*cr6+eq
-; CHECK-NEXT: rotlwi r4, r4, 4
-; CHECK-NEXT: stw r4, -4(r1)
-; CHECK-NEXT: bc 12, 4*cr6+eq, .LBB0_7
+; CHECK-NEXT: crnot 4*cr1+lt, eq
+; CHECK-NEXT: crnot 4*cr5+un, 4*cr5+eq
+; CHECK-NEXT: bc 12, 4*cr5+eq, .LBB0_7
; CHECK-NEXT: # %bb.6: # %bb18
; CHECK-NEXT: lwz r4, 0(r3)
; CHECK-NEXT: b .LBB0_8
; CHECK-NEXT: .LBB0_7:
; CHECK-NEXT: # implicit-def: $r4
; CHECK-NEXT: .LBB0_8: # %bb20
-; CHECK-NEXT: cmpwi r3, -1
+; CHECK-NEXT: cmpwi cr2, r3, -1
; CHECK-NEXT: cmpwi cr3, r4, -1
; CHECK-NEXT: cmpwi cr7, r3, 0
-; CHECK-NEXT: cmpwi cr1, r4, 0
+; CHECK-NEXT: cmpwi cr6, r4, 0
; CHECK-NEXT: # implicit-def: $x3
-; CHECK-NEXT: crand 4*cr5+eq, gt, 4*cr2+un
-; CHECK-NEXT: crand 4*cr5+gt, 4*cr3+gt, 4*cr5+lt
-; CHECK-NEXT: setnbc r4, 4*cr5+eq
-; CHECK-NEXT: stw r4, -20(r1)
-; CHECK-NEXT: bc 4, 4*cr5+eq, .LBB0_10
+; CHECK-NEXT: crand 4*cr5+gt, 4*cr2+gt, 4*cr1+lt
+; CHECK-NEXT: crand 4*cr5+lt, 4*cr3+gt, 4*cr5+un
+; CHECK-NEXT: bc 4, 4*cr5+gt, .LBB0_10
; CHECK-NEXT: # %bb.9: # %bb34
; CHECK-NEXT: ld r3, 0(r3)
; CHECK-NEXT: .LBB0_10: # %bb36
-; CHECK-NEXT: mfocrf r4, 2
-; CHECK-NEXT: cmpwi cr3, r5, 0
-; CHECK-NEXT: rotlwi r4, r4, 24
-; CHECK-NEXT: stw r4, -12(r1)
+; CHECK-NEXT: cmpwi cr2, r5, 0
; CHECK-NEXT: # implicit-def: $x4
-; CHECK-NEXT: bc 4, 4*cr5+gt, .LBB0_12
+; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_12
; CHECK-NEXT: # %bb.11: # %bb38
; CHECK-NEXT: ld r4, 0(r3)
; CHECK-NEXT: .LBB0_12: # %bb40
-; CHECK-NEXT: mcrf cr6, cr4
-; CHECK-NEXT: crnot 4*cr4+eq, 4*cr4+eq
-; CHECK-NEXT: crand 4*cr4+gt, 4*cr7+lt, 4*cr2+un
-; CHECK-NEXT: crand 4*cr4+lt, 4*cr1+lt, 4*cr5+lt
+; CHECK-NEXT: crand 4*cr6+gt, 4*cr7+lt, 4*cr1+lt
+; CHECK-NEXT: crand 4*cr6+lt, 4*cr6+lt, 4*cr5+un
+; CHECK-NEXT: crnot 4*cr6+un, 4*cr1+eq
; CHECK-NEXT: # implicit-def: $x6
-; CHECK-NEXT: bc 4, 4*cr4+lt, .LBB0_14
+; CHECK-NEXT: bc 4, 4*cr6+lt, .LBB0_14
; CHECK-NEXT: # %bb.13: # %bb48
; CHECK-NEXT: ld r6, 0(r3)
; CHECK-NEXT: .LBB0_14: # %bb50
-; CHECK-NEXT: cmpwi r5, -1
-; CHECK-NEXT: crand 4*cr4+un, 4*cr3+lt, 4*cr4+eq
+; CHECK-NEXT: cmpwi cr3, r5, -1
+; CHECK-NEXT: crand 4*cr7+lt, 4*cr2+lt, 4*cr6+un
; CHECK-NEXT: # implicit-def: $r5
-; CHECK-NEXT: bc 4, 4*cr4+gt, .LBB0_16
+; CHECK-NEXT: bc 4, 4*cr6+gt, .LBB0_16
; CHECK-NEXT: # %bb.15: # %bb52
; CHECK-NEXT: lwz r5, 0(r3)
; CHECK-NEXT: .LBB0_16: # %bb54
-; CHECK-NEXT: setnbc r7, 4*cr5+gt
-; CHECK-NEXT: stw r7, -16(r1)
-; CHECK-NEXT: mfocrf r7, 2
-; CHECK-NEXT: rotlwi r7, r7, 24
-; CHECK-NEXT: stw r7, -8(r1)
+; CHECK-NEXT: mfocrf r7, 128
+; CHECK-NEXT: stw r7, -4(r1)
; CHECK-NEXT: # implicit-def: $r7
-; CHECK-NEXT: bc 4, 4*cr4+un, .LBB0_18
+; CHECK-NEXT: bc 4, 4*cr7+lt, .LBB0_18
; CHECK-NEXT: # %bb.17: # %bb56
; CHECK-NEXT: lwz r7, 0(r3)
; CHECK-NEXT: .LBB0_18: # %bb58
-; CHECK-NEXT: crand 4*cr5+gt, 4*cr7+eq, 4*cr2+un
-; CHECK-NEXT: mcrf cr2, cr1
-; CHECK-NEXT: cmpwi cr1, r5, 1
-; CHECK-NEXT: crand lt, gt, 4*cr4+eq
-; CHECK-NEXT: # implicit-def: $x5
-; CHECK-NEXT: crand 4*cr4+eq, 4*cr3+eq, 4*cr4+eq
-; CHECK-NEXT: setnbc r8, 4*cr5+gt
-; CHECK-NEXT: crand 4*cr5+lt, 4*cr2+eq, 4*cr5+lt
-; CHECK-NEXT: crand gt, 4*cr1+lt, 4*cr4+gt
-; CHECK-NEXT: stw r8, -24(r1)
-; CHECK-NEXT: setnbc r8, 4*cr5+lt
-; CHECK-NEXT: cmpwi cr5, r7, 1
-; CHECK-NEXT: stw r8, -28(r1)
-; CHECK-NEXT: crand eq, 4*cr5+lt, 4*cr4+un
; CHECK-NEXT: lwz r6, 92(r6)
-; CHECK-NEXT: cmpwi cr6, r6, 1
-; CHECK-NEXT: crand un, 4*cr6+lt, 4*cr4+lt
-; CHECK-NEXT: bc 4, gt, .LBB0_20
+; CHECK-NEXT: crand 4*cr7+un, 4*cr3+gt, 4*cr6+un
+; CHECK-NEXT: cmpwi cr3, r5, 1
+; CHECK-NEXT: cmpwi cr4, r7, 1
+; CHECK-NEXT: crand 4*cr7+gt, 4*cr7+eq, 4*cr1+lt
+; CHECK-NEXT: # implicit-def: $x5
+; CHECK-NEXT: crand 4*cr6+un, 4*cr2+eq, 4*cr6+un
+; CHECK-NEXT: crand 4*cr5+un, 4*cr6+eq, 4*cr5+un
+; CHECK-NEXT: crand 4*cr6+gt, 4*cr3+lt, 4*cr6+gt
+; CHECK-NEXT: crand 4*cr7+lt, 4*cr4+lt, 4*cr7+lt
+; CHECK-NEXT: cmpwi r6, 1
+; CHECK-NEXT: crand 4*cr6+lt, lt, 4*cr6+lt
+; CHECK-NEXT: bc 4, 4*cr6+gt, .LBB0_20
; CHECK-NEXT: # %bb.19: # %bb68
; CHECK-NEXT: ld r5, 0(r3)
; CHECK-NEXT: .LBB0_20: # %bb70
-; CHECK-NEXT: lwz r7, -20(r1)
-; CHECK-NEXT: # implicit-def: $cr5lt
-; CHECK-NEXT: mfocrf r6, 4
-; CHECK-NEXT: xxlxor f2, f2, f2
-; CHECK-NEXT: rlwimi r6, r7, 12, 20, 20
-; CHECK-NEXT: mtocrf 4, r6
; CHECK-NEXT: ld r6, 0(r3)
-; CHECK-NEXT: lwz r8, -16(r1)
-; CHECK-NEXT: crandc 4*cr5+gt, lt, 4*cr3+eq
-; CHECK-NEXT: # implicit-def: $cr5eq
-; CHECK-NEXT: crandc 4*cr5+lt, 4*cr5+lt, 4*cr7+eq
-; CHECK-NEXT: mfocrf r7, 4
-; CHECK-NEXT: rlwimi r7, r8, 10, 22, 22
-; CHECK-NEXT: mtocrf 4, r7
-; CHECK-NEXT: lwz r7, -24(r1)
-; CHECK-NEXT: # implicit-def: $cr5un
-; CHECK-NEXT: lwz r9, -28(r1)
-; CHECK-NEXT: crandc 4*cr5+eq, 4*cr5+eq, 4*cr2+eq
-; CHECK-NEXT: isel r3, r3, r5, 4*cr5+lt
-; CHECK-NEXT: crnor 4*cr5+lt, gt, 4*cr5+lt
-; CHECK-NEXT: crnor 4*cr5+gt, eq, 4*cr5+gt
-; CHECK-NEXT: crnor 4*cr5+eq, un, 4*cr5+eq
-; CHECK-NEXT: mfocrf r5, 4
-; CHECK-NEXT: rlwimi r5, r7, 9, 23, 23
-; CHECK-NEXT: setbc r7, 4*cr4+eq
-; CHECK-NEXT: mtocrf 4, r5
-; CHECK-NEXT: setbc r5, 4*cr5+un
-; CHECK-NEXT: # implicit-def: $cr5un
-; CHECK-NEXT: mfocrf r8, 4
-; CHECK-NEXT: rlwimi r8, r9, 9, 23, 23
; CHECK-NEXT: lwz r9, -4(r1)
-; CHECK-NEXT: mtocrf 4, r8
-; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt
+; CHECK-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr7+eq
+; CHECK-NEXT: crandc 4*cr7+eq, 4*cr7+un, 4*cr2+eq
+; CHECK-NEXT: crandc 4*cr5+lt, 4*cr5+lt, 4*cr6+eq
+; CHECK-NEXT: setbc r7, 4*cr6+un
; CHECK-NEXT: setbc r8, 4*cr5+un
-; CHECK-NEXT: isel r6, 0, r6, 4*cr5+gt
+; CHECK-NEXT: lwz r12, 8(r1)
+; CHECK-NEXT: xxlxor f2, f2, f2
+; CHECK-NEXT: isel r3, r3, r5, 4*cr5+gt
+; CHECK-NEXT: setbc r5, 4*cr7+gt
+; CHECK-NEXT: crnor 4*cr5+gt, 4*cr6+gt, 4*cr5+gt
+; CHECK-NEXT: crnor 4*cr6+gt, 4*cr7+lt, 4*cr7+eq
+; CHECK-NEXT: crnor 4*cr5+lt, 4*cr6+lt, 4*cr5+lt
; CHECK-NEXT: add r5, r7, r5
; CHECK-NEXT: add r5, r8, r5
+; CHECK-NEXT: isel r3, 0, r3, 4*cr5+gt
+; CHECK-NEXT: isel r4, 0, r4, 4*cr5+lt
+; CHECK-NEXT: isel r6, 0, r6, 4*cr6+gt
; CHECK-NEXT: mtocrf 128, r9
-; CHECK-NEXT: lwz r9, -8(r1)
-; CHECK-NEXT: isel r4, 0, r4, 4*cr5+eq
-; CHECK-NEXT: iseleq r3, 0, r3
; CHECK-NEXT: mtfprd f0, r5
-; CHECK-NEXT: xscvsxddp f0, f0
-; CHECK-NEXT: mtocrf 128, r9
-; CHECK-NEXT: lwz r9, -12(r1)
-; CHECK-NEXT: lwz r12, 8(r1)
-; CHECK-NEXT: iseleq r6, 0, r6
-; CHECK-NEXT: xsmuldp f0, f0, f2
-; CHECK-NEXT: mtocrf 128, r9
+; CHECK-NEXT: isel r4, 0, r4, 4*cr5+eq
; CHECK-NEXT: mtocrf 32, r12
; CHECK-NEXT: mtocrf 16, r12
; CHECK-NEXT: mtocrf 8, r12
-; CHECK-NEXT: iseleq r4, 0, r4
+; CHECK-NEXT: iseleq r3, 0, r3
+; CHECK-NEXT: isel r6, 0, r6, 4*cr1+eq
+; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-NEXT: add r3, r6, r3
; CHECK-NEXT: add r3, r4, r3
; CHECK-NEXT: mtfprd f1, r3
+; CHECK-NEXT: xsmuldp f0, f0, f2
; CHECK-NEXT: xscvsxddp f1, f1
; CHECK-NEXT: xsadddp f1, f0, f1
; CHECK-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll b/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
index 80712411e94b8..ba81c46a738d8 100644
--- a/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
@@ -186,7 +186,7 @@ define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
; CHECK-NEXT: mtocrf 8, r12
; CHECK-NEXT: blr
; CHECK-NEXT: .LBB0_32: # %bb29
-; CHECK-NEXT: mcrf cr0, cr4
+; CHECK-NEXT: crmove eq, 4*cr4+eq
; CHECK-NEXT: cmpwi cr3, r5, 366
; CHECK-NEXT: cmpwi cr4, r3, 0
; CHECK-NEXT: li r29, 0
@@ -379,7 +379,7 @@ define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
; CHECK-BE-NEXT: mtocrf 8, r12
; CHECK-BE-NEXT: blr
; CHECK-BE-NEXT: .LBB0_32: # %bb29
-; CHECK-BE-NEXT: mcrf cr0, cr4
+; CHECK-BE-NEXT: crmove eq, 4*cr4+eq
; CHECK-BE-NEXT: cmpwi cr3, r5, 366
; CHECK-BE-NEXT: cmpwi cr4, r3, 0
; CHECK-BE-NEXT: li r29, 0
diff --git a/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll b/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll
index 5c1c1d90966fa..32f3342243904 100644
--- a/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll
@@ -30,25 +30,23 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stw r12, 8(r1)
-; CHECK-NEXT: stdu r1, -80(r1)
-; CHECK-NEXT: .cfi_def_cfa_offset 80
+; CHECK-NEXT: stdu r1, -48(r1)
+; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: .cfi_offset cr2, 8
; CHECK-NEXT: .cfi_offset cr3, 8
; CHECK-NEXT: .cfi_offset cr4, 8
-; CHECK-NEXT: std r30, 64(r1) # 8-byte Folded Spill
+; CHECK-NEXT: std r30, 32(r1) # 8-byte Folded Spill
; CHECK-NEXT: bl call_2 at notoc
; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_13
; CHECK-NEXT: # %bb.1: # %bb
; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_14
; CHECK-NEXT: # %bb.2: # %bb4
; CHECK-NEXT: cmpdi cr3, r3, 0
-; CHECK-NEXT: # implicit-def: $r30
-; CHECK-NEXT: crnot 4*cr5+lt, 4*cr3+eq
-; CHECK-NEXT: setnbc r3, 4*cr5+lt
-; CHECK-NEXT: stw r3, 60(r1)
; CHECK-NEXT: lwz r3, 0(r3)
+; CHECK-NEXT: # implicit-def: $r30
+; CHECK-NEXT: crnot 4*cr3+lt, 4*cr3+eq
; CHECK-NEXT: cmpwi cr4, r3, 0
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_3: # %bb12
@@ -76,12 +74,7 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
; CHECK-NEXT: .LBB0_8: # %bb22
; CHECK-NEXT: .LBB0_9: # %bb35
; CHECK-NEXT: .LBB0_10: # %bb27
-; CHECK-NEXT: lwz r4, 60(r1)
-; CHECK-NEXT: # implicit-def: $cr5lt
-; CHECK-NEXT: mfocrf r3, 4
-; CHECK-NEXT: rlwimi r3, r4, 12, 20, 20
-; CHECK-NEXT: mtocrf 4, r3
-; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_12
+; CHECK-NEXT: bc 4, 4*cr3+lt, .LBB0_12
; CHECK-NEXT: # %bb.11: # %bb28
; CHECK-NEXT: .LBB0_12: # %bb29
; CHECK-NEXT: .LBB0_13: # %bb3
@@ -93,16 +86,16 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
; CHECK-BE-NEXT: mflr r0
; CHECK-BE-NEXT: std r0, 16(r1)
; CHECK-BE-NEXT: stw r12, 8(r1)
-; CHECK-BE-NEXT: stdu r1, -160(r1)
-; CHECK-BE-NEXT: .cfi_def_cfa_offset 160
+; CHECK-BE-NEXT: stdu r1, -144(r1)
+; CHECK-BE-NEXT: .cfi_def_cfa_offset 144
; CHECK-BE-NEXT: .cfi_offset lr, 16
; CHECK-BE-NEXT: .cfi_offset r29, -24
; CHECK-BE-NEXT: .cfi_offset r30, -16
; CHECK-BE-NEXT: .cfi_offset cr2, 8
; CHECK-BE-NEXT: .cfi_offset cr2, 8
; CHECK-BE-NEXT: .cfi_offset cr2, 8
-; CHECK-BE-NEXT: std r29, 136(r1) # 8-byte Folded Spill
-; CHECK-BE-NEXT: std r30, 144(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT: std r29, 120(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT: std r30, 128(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: bl call_2
; CHECK-BE-NEXT: nop
; CHECK-BE-NEXT: bc 12, 4*cr5+lt, .LBB0_13
@@ -110,12 +103,10 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
; CHECK-BE-NEXT: bc 4, 4*cr5+lt, .LBB0_14
; CHECK-BE-NEXT: # %bb.2: # %bb4
; CHECK-BE-NEXT: cmpdi cr3, r3, 0
+; CHECK-BE-NEXT: lwz r3, 0(r3)
; CHECK-BE-NEXT: addis r30, r2, call_1 at toc@ha
; CHECK-BE-NEXT: # implicit-def: $r29
-; CHECK-BE-NEXT: crnot 4*cr5+lt, 4*cr3+eq
-; CHECK-BE-NEXT: setnbc r3, 4*cr5+lt
-; CHECK-BE-NEXT: stw r3, 132(r1)
-; CHECK-BE-NEXT: lwz r3, 0(r3)
+; CHECK-BE-NEXT: crnot 4*cr3+lt, 4*cr3+eq
; CHECK-BE-NEXT: cmpwi cr4, r3, 0
; CHECK-BE-NEXT: .p2align 4
; CHECK-BE-NEXT: .LBB0_3: # %bb12
@@ -145,12 +136,7 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
; CHECK-BE-NEXT: .LBB0_8: # %bb22
; CHECK-BE-NEXT: .LBB0_9: # %bb35
; CHECK-BE-NEXT: .LBB0_10: # %bb27
-; CHECK-BE-NEXT: lwz r4, 132(r1)
-; CHECK-BE-NEXT: # implicit-def: $cr5lt
-; CHECK-BE-NEXT: mfocrf r3, 4
-; CHECK-BE-NEXT: rlwimi r3, r4, 12, 20, 20
-; CHECK-BE-NEXT: mtocrf 4, r3
-; CHECK-BE-NEXT: bc 4, 4*cr5+lt, .LBB0_12
+; CHECK-BE-NEXT: bc 4, 4*cr3+lt, .LBB0_12
; CHECK-BE-NEXT: # %bb.11: # %bb28
; CHECK-BE-NEXT: .LBB0_12: # %bb29
; CHECK-BE-NEXT: .LBB0_13: # %bb3
diff --git a/llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll b/llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
index 1dcef38f634f7..cfa9315896af3 100644
--- a/llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
+++ b/llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
@@ -20,28 +20,24 @@ declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
define void @ass_pair(ptr %ptr, <16 x i8> %vc) {
; CHECK-LABEL: ass_pair:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmr v3, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: stxv v2, 16(r3)
-; CHECK-NEXT: stxv v3, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-NOMMA-LABEL: ass_pair:
; CHECK-NOMMA: # %bb.0: # %entry
-; CHECK-NOMMA-NEXT: vmr v3, v2
+; CHECK-NOMMA-NEXT: stxv v2, 0(r3)
; CHECK-NOMMA-NEXT: stxv v2, 16(r3)
-; CHECK-NOMMA-NEXT: stxv v3, 0(r3)
; CHECK-NOMMA-NEXT: blr
;
; CHECK-BE-LABEL: ass_pair:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vmr v3, v2
; CHECK-BE-NEXT: stxv v2, 16(r3)
; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
;
; CHECK-BE-NOMMA-LABEL: ass_pair:
; CHECK-BE-NOMMA: # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT: vmr v3, v2
; CHECK-BE-NOMMA-NEXT: stxv v2, 16(r3)
; CHECK-BE-NOMMA-NEXT: stxv v2, 0(r3)
; CHECK-BE-NOMMA-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll b/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
index 0146dc8a1c163..a958bb346ae20 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
@@ -6,9 +6,8 @@
define void @copy_novsrp() local_unnamed_addr {
; CHECK-LABEL: copy_novsrp:
; CHECK: # %bb.0: # %dmblvi_entry
-; CHECK-NEXT: xxlxor v2, v2, v2
+; CHECK-NEXT: xxlxor vs3, vs3, vs3
; CHECK-NEXT: xxlxor vs0, vs0, vs0
-; CHECK-NEXT: xxlor vs3, v2, v2
; CHECK-NEXT: stxv vs0, 0(0)
dmblvi_entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> undef, <16 x i8> undef, <16 x i8> zeroinitializer)
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll b/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
index 940075d986731..3823cce421440 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
@@ -31,45 +31,36 @@ define void @acc_regalloc(ptr %arg, ptr %arg1, ptr %arg2) local_unnamed_addr {
; CHECK-NEXT: addi r6, r6, 2
; CHECK-NEXT: lxv vs0, 16(0)
; CHECK-NEXT: lxv vs1, -64(r5)
-; CHECK-NEXT: xxlxor v7, v7, v7
-; CHECK-NEXT: vmr v9, v0
-; CHECK-NEXT: xxlxor v10, v10, v10
+; CHECK-NEXT: xxlxor vs7, vs7, vs7
+; CHECK-NEXT: xxlor vs3, v0, v0
+; CHECK-NEXT: xxlxor vs2, vs2, vs2
+; CHECK-NEXT: xxlxor vs12, vs12, vs12
; CHECK-NEXT: mulld r6, r6, r3
-; CHECK-NEXT: xvmaddadp v7, vs0, v5
-; CHECK-NEXT: xvmuldp v6, vs0, v2
+; CHECK-NEXT: xxlor vs10, v2, v2
+; CHECK-NEXT: xxlor vs4, v2, v2
+; CHECK-NEXT: xxlor vs8, vs10, vs10
+; CHECK-NEXT: xxlor vs10, v1, v1
+; CHECK-NEXT: xvmaddadp vs7, vs0, v5
+; CHECK-NEXT: xvmuldp vs6, vs0, v2
; CHECK-NEXT: lxv vs0, -16(r5)
-; CHECK-NEXT: xvmaddadp v9, vs1, v2
-; CHECK-NEXT: xxlxor v8, v8, v8
-; CHECK-NEXT: xvmaddadp v7, v2, v2
-; CHECK-NEXT: xvmaddadp v6, v2, v2
-; CHECK-NEXT: lxvdsx v14, r6, r4
+; CHECK-NEXT: xvmaddadp vs3, vs1, v2
+; CHECK-NEXT: xvmaddadp vs2, vs1, vs2
+; CHECK-NEXT: lxvdsx v6, r6, r4
; CHECK-NEXT: li r6, 0
-; CHECK-NEXT: xvmaddadp v8, vs1, v8
-; CHECK-NEXT: xvmaddadp v10, vs0, v10
-; CHECK-NEXT: xvmuldp v3, vs1, v14
-; CHECK-NEXT: xvmuldp v11, vs0, v14
-; CHECK-NEXT: xvmuldp vs5, v14, v2
-; CHECK-NEXT: xvmuldp v13, v4, v14
+; CHECK-NEXT: xvmaddadp vs7, v2, v2
+; CHECK-NEXT: xvmaddadp vs6, v2, v2
+; CHECK-NEXT: xvmaddadp vs12, vs0, vs12
+; CHECK-NEXT: xvmuldp v3, vs1, v6
+; CHECK-NEXT: xvmuldp vs11, v4, v6
+; CHECK-NEXT: xvmuldp vs13, vs0, v6
+; CHECK-NEXT: xvmuldp vs5, v6, v2
; CHECK-NEXT: xxlor vs0, v2, v2
-; CHECK-NEXT: vmr v12, v2
-; CHECK-NEXT: xxlor vs14, v10, v10
-; CHECK-NEXT: xxlor vs4, v2, v2
-; CHECK-NEXT: # kill: def $vsrp2 killed $vsrp2 def $uacc1
-; CHECK-NEXT: xxlor vs6, v6, v6
-; CHECK-NEXT: xxlor vs7, v7, v7
-; CHECK-NEXT: xxlor vs8, v12, v12
-; CHECK-NEXT: xxlor vs9, v13, v13
-; CHECK-NEXT: vmr v12, v1
+; CHECK-NEXT: xxlor vs14, vs12, vs12
+; CHECK-NEXT: xxlor vs12, v2, v2
; CHECK-NEXT: xxlor vs1, v3, v3
-; CHECK-NEXT: xxlor vs2, v8, v8
-; CHECK-NEXT: xxlor vs3, v9, v9
-; CHECK-NEXT: xxlor vs15, v11, v11
-; CHECK-NEXT: vmr v10, v2
-; CHECK-NEXT: xxlor vs10, v12, v12
-; CHECK-NEXT: xxlor vs11, v13, v13
+; CHECK-NEXT: xxlor vs9, vs11, vs11
+; CHECK-NEXT: xxlor vs15, vs13, vs13
; CHECK-NEXT: xxmtacc acc1
-; CHECK-NEXT: xxlor vs12, v10, v10
-; CHECK-NEXT: xxlor vs13, v11, v11
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xxmtacc acc2
; CHECK-NEXT: xxmtacc acc3
diff --git a/llvm/test/CodeGen/PowerPC/pr45709.ll b/llvm/test/CodeGen/PowerPC/pr45709.ll
index 3a26173965467..5448418aaf3c8 100644
--- a/llvm/test/CodeGen/PowerPC/pr45709.ll
+++ b/llvm/test/CodeGen/PowerPC/pr45709.ll
@@ -40,6 +40,7 @@ define dso_local void @_ZN1a1bEv(<4 x float> %in) local_unnamed_addr #0 align 2
; CHECK-NEXT: lvx v2, 0, r3
; CHECK-NEXT: addi r3, r1, -16
; CHECK-NEXT: stvx v2, 0, r3
+; CHECK-NEXT: lfs f0, -16(r1)
; CHECK-NEXT: .LBB0_6:
; CHECK-NEXT: blr
br i1 undef, label %7, label %1
diff --git a/llvm/test/CodeGen/PowerPC/spe.ll b/llvm/test/CodeGen/PowerPC/spe.ll
index f963d145bda3c..14ea241133d30 100644
--- a/llvm/test/CodeGen/PowerPC/spe.ll
+++ b/llvm/test/CodeGen/PowerPC/spe.ll
@@ -1422,8 +1422,8 @@ define i1 @test_dcmpge(double %a, double %b) #0 {
; SPE-NEXT: efdcmpeq 0, 4, 4
; SPE-NEXT: efdcmpeq 1, 3, 3
; SPE-NEXT: efdcmplt 5, 3, 4
-; SPE-NEXT: crand 24, 5, 1
-; SPE-NEXT: crorc 20, 21, 24
+; SPE-NEXT: crand 20, 5, 1
+; SPE-NEXT: crorc 20, 21, 20
; SPE-NEXT: bc 12, 20, .LBB47_2
; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: ori 3, 7, 0
diff --git a/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll b/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
index 778edba2719a6..e2bbb04cf532a 100644
--- a/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
+++ b/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
@@ -43,24 +43,24 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
; PPC32-NEXT: mulhwu. 26, 5, 8
; PPC32-NEXT: mcrf 5, 0
; PPC32-NEXT: stw 23, 28(1) # 4-byte Folded Spill
-; PPC32-NEXT: crnor 28, 30, 10
+; PPC32-NEXT: crnor 20, 30, 10
; PPC32-NEXT: stw 29, 52(1) # 4-byte Folded Spill
-; PPC32-NEXT: cmpwi 2, 9, 0
+; PPC32-NEXT: cmpwi 7, 9, 0
; PPC32-NEXT: mulhwu. 26, 3, 10
; PPC32-NEXT: mcrf 6, 0
-; PPC32-NEXT: cmpwi 3, 3, 0
+; PPC32-NEXT: cmpwi 2, 3, 0
; PPC32-NEXT: stw 24, 32(1) # 4-byte Folded Spill
-; PPC32-NEXT: crnor 29, 10, 14
+; PPC32-NEXT: crnor 21, 30, 10
; PPC32-NEXT: stw 25, 36(1) # 4-byte Folded Spill
; PPC32-NEXT: mulhwu. 26, 9, 4
; PPC32-NEXT: stw 27, 44(1) # 4-byte Folded Spill
-; PPC32-NEXT: crorc 28, 28, 6
+; PPC32-NEXT: crorc 20, 20, 6
; PPC32-NEXT: stw 28, 48(1) # 4-byte Folded Spill
-; PPC32-NEXT: crorc 20, 28, 22
+; PPC32-NEXT: crorc 21, 21, 26
; PPC32-NEXT: stw 30, 56(1) # 4-byte Folded Spill
; PPC32-NEXT: mulhwu 0, 6, 10
; PPC32-NEXT: stw 12, 20(1)
-; PPC32-NEXT: crorc 21, 29, 26
+; PPC32-NEXT: crorc 20, 20, 22
; PPC32-NEXT: crorc 21, 21, 2
; PPC32-NEXT: li 11, 0
; PPC32-NEXT: mullw 26, 5, 10
@@ -102,7 +102,7 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
; PPC32-NEXT: addc 4, 7, 3
; PPC32-NEXT: adde 3, 8, 9
; PPC32-NEXT: cror 21, 22, 21
-; PPC32-NEXT: cmplw 4, 7
+; PPC32-NEXT: cmplw 4, 7
; PPC32-NEXT: cmplw 1, 3, 8
; PPC32-NEXT: lwz 12, 20(1)
; PPC32-NEXT: cror 20, 21, 20
@@ -115,10 +115,9 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
; PPC32-NEXT: bc 12, 20, .LBB0_1
; PPC32-NEXT: b .LBB0_2
; PPC32-NEXT: .LBB0_1: # %start
-; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: li 7, 0
; PPC32-NEXT: .LBB0_2: # %start
; PPC32-NEXT: mtcrf 32, 12 # cr2
-; PPC32-NEXT: mtcrf 16, 12 # cr3
; PPC32-NEXT: lwz 30, 56(1) # 4-byte Folded Reload
; PPC32-NEXT: lwz 29, 52(1) # 4-byte Folded Reload
; PPC32-NEXT: lwz 28, 48(1) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll b/llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll
index c6dfa12db0405..1579bcdb6e852 100644
--- a/llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll
+++ b/llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll
@@ -897,13 +897,13 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: mr 21, 8
; LE-32BIT-NEXT: or 8, 14, 3
; LE-32BIT-NEXT: srw 14, 6, 31
-; LE-32BIT-NEXT: crnand 28, 4, 20
+; LE-32BIT-NEXT: crnand 21, 4, 20
; LE-32BIT-NEXT: srw 31, 6, 30
; LE-32BIT-NEXT: or 24, 0, 24
; LE-32BIT-NEXT: slw 0, 7, 15
; LE-32BIT-NEXT: mr 23, 7
; LE-32BIT-NEXT: or 17, 17, 14
-; LE-32BIT-NEXT: bc 12, 28, .LBB9_2
+; LE-32BIT-NEXT: bc 12, 21, .LBB9_2
; LE-32BIT-NEXT: # %bb.1:
; LE-32BIT-NEXT: ori 14, 31, 0
; LE-32BIT-NEXT: b .LBB9_3
@@ -945,7 +945,7 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: srw 0, 10, 30
; LE-32BIT-NEXT: srw 5, 10, 5
; LE-32BIT-NEXT: or 3, 0, 3
-; LE-32BIT-NEXT: bc 12, 28, .LBB9_5
+; LE-32BIT-NEXT: bc 12, 21, .LBB9_5
; LE-32BIT-NEXT: # %bb.4:
; LE-32BIT-NEXT: ori 0, 17, 0
; LE-32BIT-NEXT: b .LBB9_6
@@ -982,11 +982,11 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: srw 30, 21, 30
; LE-32BIT-NEXT: lwz 8, 24(1) # 4-byte Folded Reload
; LE-32BIT-NEXT: slw 21, 29, 16
-; LE-32BIT-NEXT: cmplwi 7, 16, 64
+; LE-32BIT-NEXT: cmplwi 2, 16, 64
; LE-32BIT-NEXT: cmplwi 3, 16, 0
; LE-32BIT-NEXT: li 16, 0
; LE-32BIT-NEXT: srw 18, 6, 0
-; LE-32BIT-NEXT: bc 12, 28, .LBB9_14
+; LE-32BIT-NEXT: bc 12, 8, .LBB9_14
; LE-32BIT-NEXT: # %bb.13:
; LE-32BIT-NEXT: ori 0, 16, 0
; LE-32BIT-NEXT: b .LBB9_15
@@ -994,7 +994,7 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: addi 0, 21, 0
; LE-32BIT-NEXT: .LBB9_15:
; LE-32BIT-NEXT: lwz 21, 60(1) # 4-byte Folded Reload
-; LE-32BIT-NEXT: bc 12, 28, .LBB9_16
+; LE-32BIT-NEXT: bc 12, 8, .LBB9_16
; LE-32BIT-NEXT: b .LBB9_17
; LE-32BIT-NEXT: .LBB9_16:
; LE-32BIT-NEXT: addi 4, 7, 0
@@ -1013,7 +1013,7 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: .LBB9_20:
; LE-32BIT-NEXT: addi 8, 21, 0
; LE-32BIT-NEXT: .LBB9_21:
-; LE-32BIT-NEXT: cmplwi 2, 31, 0
+; LE-32BIT-NEXT: cmplwi 7, 31, 0
; LE-32BIT-NEXT: bc 12, 20, .LBB9_23
; LE-32BIT-NEXT: # %bb.22:
; LE-32BIT-NEXT: ori 26, 19, 0
@@ -1043,7 +1043,7 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: addi 29, 7, 0
; LE-32BIT-NEXT: .LBB9_32:
; LE-32BIT-NEXT: lwz 7, 44(1) # 4-byte Folded Reload
-; LE-32BIT-NEXT: bc 12, 10, .LBB9_33
+; LE-32BIT-NEXT: bc 12, 30, .LBB9_33
; LE-32BIT-NEXT: b .LBB9_34
; LE-32BIT-NEXT: .LBB9_33:
; LE-32BIT-NEXT: addi 25, 12, 0
@@ -1066,7 +1066,7 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: .LBB9_40:
; LE-32BIT-NEXT: addi 3, 10, 0
; LE-32BIT-NEXT: .LBB9_41:
-; LE-32BIT-NEXT: bc 12, 28, .LBB9_43
+; LE-32BIT-NEXT: bc 12, 8, .LBB9_43
; LE-32BIT-NEXT: # %bb.42:
; LE-32BIT-NEXT: ori 5, 20, 0
; LE-32BIT-NEXT: b .LBB9_43
@@ -1081,7 +1081,7 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: ori 28, 18, 0
; LE-32BIT-NEXT: b .LBB9_47
; LE-32BIT-NEXT: .LBB9_47:
-; LE-32BIT-NEXT: bc 12, 28, .LBB9_49
+; LE-32BIT-NEXT: bc 12, 8, .LBB9_49
; LE-32BIT-NEXT: # %bb.48:
; LE-32BIT-NEXT: ori 27, 16, 0
; LE-32BIT-NEXT: b .LBB9_49
@@ -1101,7 +1101,7 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: .LBB9_54:
; LE-32BIT-NEXT: addi 5, 11, 0
; LE-32BIT-NEXT: .LBB9_55:
-; LE-32BIT-NEXT: bc 12, 10, .LBB9_56
+; LE-32BIT-NEXT: bc 12, 30, .LBB9_56
; LE-32BIT-NEXT: b .LBB9_57
; LE-32BIT-NEXT: .LBB9_56:
; LE-32BIT-NEXT: addi 28, 10, 0
@@ -1478,7 +1478,7 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: srw 24, 6, 24
; LE-32BIT-NEXT: or 10, 14, 3
; LE-32BIT-NEXT: slw 14, 5, 31
-; LE-32BIT-NEXT: crnand 28, 4, 20
+; LE-32BIT-NEXT: crnand 21, 4, 20
; LE-32BIT-NEXT: slw 31, 5, 30
; LE-32BIT-NEXT: or 24, 0, 24
; LE-32BIT-NEXT: mr 3, 7
@@ -1486,7 +1486,7 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: srw 0, 7, 22
; LE-32BIT-NEXT: lwz 7, 24(1) # 4-byte Folded Reload
; LE-32BIT-NEXT: or 17, 17, 14
-; LE-32BIT-NEXT: bc 12, 28, .LBB10_2
+; LE-32BIT-NEXT: bc 12, 21, .LBB10_2
; LE-32BIT-NEXT: # %bb.1:
; LE-32BIT-NEXT: ori 14, 31, 0
; LE-32BIT-NEXT: b .LBB10_3
@@ -1506,7 +1506,7 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: lwz 3, 40(1) # 4-byte Folded Reload
; LE-32BIT-NEXT: or 4, 4, 31
; LE-32BIT-NEXT: slw 0, 11, 0
-; LE-32BIT-NEXT: cmplwi 3, 15, 0
+; LE-32BIT-NEXT: cmplwi 2, 15, 64
; LE-32BIT-NEXT: srw 31, 6, 3
; LE-32BIT-NEXT: or 27, 27, 31
; LE-32BIT-NEXT: srw 31, 12, 25
@@ -1531,7 +1531,7 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: slw 24, 11, 16
; LE-32BIT-NEXT: lwz 10, 32(1) # 4-byte Folded Reload
; LE-32BIT-NEXT: or 3, 0, 3
-; LE-32BIT-NEXT: bc 12, 28, .LBB10_8
+; LE-32BIT-NEXT: bc 12, 21, .LBB10_8
; LE-32BIT-NEXT: # %bb.7:
; LE-32BIT-NEXT: ori 0, 17, 0
; LE-32BIT-NEXT: b .LBB10_9
@@ -1554,7 +1554,7 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: or 4, 21, 4
; LE-32BIT-NEXT: slw 21, 11, 31
; LE-32BIT-NEXT: srw 20, 12, 15
-; LE-32BIT-NEXT: cmplwi 7, 15, 64
+; LE-32BIT-NEXT: cmplwi 3, 15, 0
; LE-32BIT-NEXT: li 15, 0
; LE-32BIT-NEXT: or 27, 21, 27
; LE-32BIT-NEXT: bc 12, 20, .LBB10_14
@@ -1567,7 +1567,7 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: mr 16, 9
; LE-32BIT-NEXT: lwz 9, 52(1) # 4-byte Folded Reload
; LE-32BIT-NEXT: slw 18, 5, 0
-; LE-32BIT-NEXT: bc 12, 28, .LBB10_17
+; LE-32BIT-NEXT: bc 12, 8, .LBB10_17
; LE-32BIT-NEXT: # %bb.16:
; LE-32BIT-NEXT: ori 0, 15, 0
; LE-32BIT-NEXT: b .LBB10_18
@@ -1602,7 +1602,7 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: .LBB10_26:
; LE-32BIT-NEXT: addi 30, 29, 0
; LE-32BIT-NEXT: .LBB10_27:
-; LE-32BIT-NEXT: bc 12, 28, .LBB10_28
+; LE-32BIT-NEXT: bc 12, 8, .LBB10_28
; LE-32BIT-NEXT: b .LBB10_29
; LE-32BIT-NEXT: .LBB10_28:
; LE-32BIT-NEXT: addi 28, 26, 0
@@ -1637,13 +1637,13 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: .LBB10_39:
; LE-32BIT-NEXT: addi 3, 11, 0
; LE-32BIT-NEXT: .LBB10_40:
-; LE-32BIT-NEXT: cmplwi 2, 31, 0
+; LE-32BIT-NEXT: cmplwi 7, 31, 0
; LE-32BIT-NEXT: bc 12, 24, .LBB10_42
; LE-32BIT-NEXT: # %bb.41:
; LE-32BIT-NEXT: ori 27, 18, 0
; LE-32BIT-NEXT: b .LBB10_42
; LE-32BIT-NEXT: .LBB10_42:
-; LE-32BIT-NEXT: bc 12, 28, .LBB10_44
+; LE-32BIT-NEXT: bc 12, 8, .LBB10_44
; LE-32BIT-NEXT: # %bb.43:
; LE-32BIT-NEXT: ori 26, 22, 0
; LE-32BIT-NEXT: b .LBB10_45
@@ -1660,7 +1660,7 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: ori 3, 28, 0
; LE-32BIT-NEXT: b .LBB10_49
; LE-32BIT-NEXT: .LBB10_49:
-; LE-32BIT-NEXT: bc 12, 10, .LBB10_50
+; LE-32BIT-NEXT: bc 12, 30, .LBB10_50
; LE-32BIT-NEXT: b .LBB10_51
; LE-32BIT-NEXT: .LBB10_50:
; LE-32BIT-NEXT: addi 25, 12, 0
@@ -1673,14 +1673,14 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: .LBB10_53:
; LE-32BIT-NEXT: addi 24, 7, 0
; LE-32BIT-NEXT: .LBB10_54:
-; LE-32BIT-NEXT: bc 12, 28, .LBB10_56
+; LE-32BIT-NEXT: bc 12, 8, .LBB10_56
; LE-32BIT-NEXT: # %bb.55:
; LE-32BIT-NEXT: ori 7, 15, 0
; LE-32BIT-NEXT: b .LBB10_57
; LE-32BIT-NEXT: .LBB10_56:
; LE-32BIT-NEXT: addi 7, 23, 0
; LE-32BIT-NEXT: .LBB10_57:
-; LE-32BIT-NEXT: bc 12, 10, .LBB10_58
+; LE-32BIT-NEXT: bc 12, 30, .LBB10_58
; LE-32BIT-NEXT: b .LBB10_59
; LE-32BIT-NEXT: .LBB10_58:
; LE-32BIT-NEXT: addi 27, 11, 0
@@ -2087,7 +2087,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: or 19, 18, 19
; LE-32BIT-NEXT: cmpwi 6, 31, 1
; LE-32BIT-NEXT: sraw 18, 12, 31
-; LE-32BIT-NEXT: crand 28, 4, 20
+; LE-32BIT-NEXT: crand 21, 4, 20
; LE-32BIT-NEXT: srawi 14, 12, 31
; LE-32BIT-NEXT: sraw 31, 12, 30
; LE-32BIT-NEXT: or 3, 21, 3
@@ -2099,7 +2099,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: .LBB11_10:
; LE-32BIT-NEXT: addi 28, 17, 0
; LE-32BIT-NEXT: .LBB11_11:
-; LE-32BIT-NEXT: bc 12, 28, .LBB11_13
+; LE-32BIT-NEXT: bc 12, 21, .LBB11_13
; LE-32BIT-NEXT: # %bb.12:
; LE-32BIT-NEXT: ori 18, 14, 0
; LE-32BIT-NEXT: b .LBB11_14
@@ -2158,8 +2158,9 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: ori 24, 22, 0
; LE-32BIT-NEXT: b .LBB11_21
; LE-32BIT-NEXT: .LBB11_21:
-; LE-32BIT-NEXT: cmplwi 2, 19, 0
-; LE-32BIT-NEXT: bc 12, 10, .LBB11_22
+; LE-32BIT-NEXT: cmplwi 7, 19, 0
+; LE-32BIT-NEXT: cmplwi 2, 16, 64
+; LE-32BIT-NEXT: bc 12, 30, .LBB11_22
; LE-32BIT-NEXT: b .LBB11_23
; LE-32BIT-NEXT: .LBB11_22:
; LE-32BIT-NEXT: addi 3, 6, 0
@@ -2171,7 +2172,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: or 26, 0, 26
; LE-32BIT-NEXT: srw 0, 7, 30
; LE-32BIT-NEXT: or 11, 0, 23
-; LE-32BIT-NEXT: bc 12, 28, .LBB11_25
+; LE-32BIT-NEXT: bc 12, 21, .LBB11_25
; LE-32BIT-NEXT: # %bb.24:
; LE-32BIT-NEXT: ori 0, 14, 0
; LE-32BIT-NEXT: b .LBB11_26
@@ -2184,12 +2185,11 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: lwz 4, 52(1) # 4-byte Folded Reload
; LE-32BIT-NEXT: or 5, 0, 5
; LE-32BIT-NEXT: lwz 0, 56(1) # 4-byte Folded Reload
-; LE-32BIT-NEXT: cmplwi 7, 16, 64
; LE-32BIT-NEXT: slw 23, 6, 15
; LE-32BIT-NEXT: srw 22, 17, 4
; LE-32BIT-NEXT: li 15, 0
; LE-32BIT-NEXT: sraw 21, 12, 0
-; LE-32BIT-NEXT: bc 12, 28, .LBB11_28
+; LE-32BIT-NEXT: bc 12, 8, .LBB11_28
; LE-32BIT-NEXT: # %bb.27:
; LE-32BIT-NEXT: ori 0, 15, 0
; LE-32BIT-NEXT: b .LBB11_29
@@ -2229,7 +2229,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: addi 25, 6, 0
; LE-32BIT-NEXT: .LBB11_41:
; LE-32BIT-NEXT: lwz 6, 44(1) # 4-byte Folded Reload
-; LE-32BIT-NEXT: bc 12, 28, .LBB11_43
+; LE-32BIT-NEXT: bc 12, 8, .LBB11_43
; LE-32BIT-NEXT: # %bb.42:
; LE-32BIT-NEXT: ori 8, 27, 0
; LE-32BIT-NEXT: ori 5, 23, 0
@@ -2295,7 +2295,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: addi 3, 16, 0
; LE-32BIT-NEXT: .LBB11_66:
; LE-32BIT-NEXT: stw 4, 8(18)
-; LE-32BIT-NEXT: bc 12, 28, .LBB11_68
+; LE-32BIT-NEXT: bc 12, 8, .LBB11_68
; LE-32BIT-NEXT: # %bb.67:
; LE-32BIT-NEXT: ori 27, 15, 0
; LE-32BIT-NEXT: b .LBB11_69
@@ -2316,7 +2316,7 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
; LE-32BIT-NEXT: .LBB11_74:
; LE-32BIT-NEXT: addi 8, 9, 0
; LE-32BIT-NEXT: .LBB11_75:
-; LE-32BIT-NEXT: bc 12, 10, .LBB11_77
+; LE-32BIT-NEXT: bc 12, 30, .LBB11_77
; LE-32BIT-NEXT: # %bb.76:
; LE-32BIT-NEXT: ori 28, 26, 0
; LE-32BIT-NEXT: b .LBB11_78
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