[PATCH] D140665: [SelectionDAG][RISCV][X86][AArch64][AMDGPU][PowerPC] Improve SimplifyDemandedBits for SHL with NUW/NSW flags.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

In D140665#4017550 <https://reviews.llvm.org/D140665#4017550>, @spatel wrote:

> It's a bug if we are both propagating flags and not accounting for them - we've definitely caught cases like that in IR.
>
> I agree that it seems like the better choice would be to ignore/drop flags (the alternative is that flags could penalize optimization). But it's also possible that changing it could cause missed folds because we lost information by dropping flags. We probably just need to experiment and see what falls out from it.

I'm not sure what this is trying to fix originally,
but i think the test changes clearly show that we should be going in the opposite direction.



================
Comment at: llvm/test/CodeGen/AArch64/arm64-shifted-sext.ll:199
+; CHECK-NEXT:    add w8, w0, #1
+; CHECK-NEXT:    and w8, w8, #0xffff
+; CHECK-NEXT:    lsl w0, w8, #16
----------------
This seems to be a regression


================
Comment at: llvm/test/CodeGen/AMDGPU/shl.ll:492
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-NEXT:    s_and_b32 s4, s4, 15
 ; VI-NEXT:    s_lshl_b32 s4, s4, 12
----------------
arsenm wrote:
> This is worse
This seems to be a regression


================
Comment at: llvm/test/CodeGen/RISCV/rv64i-complex-float.ll:23
 ; CHECK-NEXT:    call __addsf3 at plt
+; CHECK-NEXT:    andi a0, a0, -1
 ; CHECK-NEXT:    slli a0, a0, 32
----------------
This seems to be a regression


================
Comment at: llvm/test/CodeGen/X86/parity.ll:404
 
 define i16 @parity_16_shift(i16 %0) {
 ; X86-NOPOPCNT-LABEL: parity_16_shift:
----------------
This seems to be a massive regression


================
Comment at: llvm/test/CodeGen/X86/parity.ll:533
 
 define i32 @parity_32_shift(i32 %0) {
 ; X86-NOPOPCNT-LABEL: parity_32_shift:
----------------
This seems to be a massive regression


================
Comment at: llvm/test/CodeGen/X86/parity.ll:657
 
 define i64 @parity_64_shift(i64 %0) {
 ; X86-NOPOPCNT-LABEL: parity_64_shift:
----------------
This seems to be a massive regression


================
Comment at: llvm/test/CodeGen/X86/setcc.ll:76
 
 define i32 @t4(i32 %a) {
 ; X86-LABEL: t4:
----------------
This seems to be a regression


================
Comment at: llvm/test/CodeGen/X86/split-store.ll:176
 
 define void @int12_int12_pair(i12 signext %tmp1, i12 signext %tmp2, ptr %ref.tmp) {
 ; CHECK-LABEL: int12_int12_pair:
----------------
This seems to be a regression


================
Comment at: llvm/test/CodeGen/X86/split-store.ll:197
 
 define void @int7_int7_pair(i7 signext %tmp1, i7 signext %tmp2, ptr %ref.tmp) {
 ; CHECK-LABEL: int7_int7_pair:
----------------
This seems to be a regression


================
Comment at: llvm/test/CodeGen/X86/split-store.ll:217
 
 define void @int1_int1_pair(i1 signext %tmp1, i1 signext %tmp2, ptr %ref.tmp) {
 ; CHECK-LABEL: int1_int1_pair:
----------------
This seems to be a regression


================
Comment at: llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll:151
 
 define <8 x i32> @PR46393(<8 x i16> %a0, i8 %a1) {
 ; X86-LABEL: PR46393:
----------------
This seems to be a regression


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140665/new/

https://reviews.llvm.org/D140665