[PATCH] D140682: [PowerPC][NFC] add test case for ShouldTrackLaneMasks

[Ting Wang via Phabricator via llvm-commits]

tingwang created this revision.
tingwang added reviewers: shchenz, nemanjai, PowerPC.
tingwang added a project: LLVM.
Herald added a project: All.
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Show motivation case for ShouldTrackLaneMasks. Enable ShouldTrackLaneMasks will eliminate the spill.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140682

Files:
  llvm/test/CodeGen/PowerPC/track-lane-masks.ll


Index: llvm/test/CodeGen/PowerPC/track-lane-masks.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/track-lane-masks.ll
@@ -0,0 +1,68 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu     \
+; RUN:   -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names            \
+; RUN:   -ppc-track-subreg-liveness=true < %s | FileCheck -check-prefix=CHECK-TRACK %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu     \
+; RUN:   -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names            \
+; RUN:   -ppc-track-subreg-liveness=false < %s | FileCheck -check-prefix=CHECK-NOTRACK %s
+
+%struct = type { i32, i32 }
+
+define internal fastcc ptr @foo(i32 %mp.4.val, ptr %ml, ptr %bm, ptr %vtable, ptr %etable) unnamed_addr {
+; CHECK-TRACK-LABEL: foo:
+; CHECK-TRACK: std {{r[0-9]+}}, {{[0-9]+}}({{r[0-9]+}}) # {{[0-9]+}}-byte Folded Spill
+; CHECK-NOTRACK-LABEL: foo:
+; CHECK-NOTRACK: std {{r[0-9]+}}, {{[0-9]+}}({{r[0-9]+}}) # {{[0-9]+}}-byte Folded Spill
+entry:
+  %0 = alloca i8, i64 poison, align 16
+  %1 = alloca i8, i64 poison, align 16
+  %wide.trip.count = zext i32 %mp.4.val to i64
+  %n.vec = and i64 %wide.trip.count, 4294967292
+  br label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %entry
+  %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
+  %2 = shl i64 %index, 3
+  %next.gep = getelementptr i8, ptr %ml, i64 %2
+  %3 = shl i64 %index, 3
+  %4 = or i64 %3, 8
+  %next.gep3 = getelementptr i8, ptr %ml, i64 %4
+  %5 = shl i64 %index, 3
+  %6 = or i64 %5, 24
+  %next.gep5 = getelementptr i8, ptr %ml, i64 %6
+  %induction8 = or i64 %index, 3
+  %7 = load i32, ptr %next.gep3, align 4
+  %8 = load i32, ptr %next.gep5, align 4
+  %9 = zext i32 %7 to i64
+  %10 = zext i32 %8 to i64
+  %11 = getelementptr inbounds ptr, ptr %vtable, i64 %9
+  %12 = getelementptr inbounds ptr, ptr %vtable, i64 %10
+  %13 = load ptr, ptr %11, align 8
+  %14 = load ptr, ptr %12, align 8
+  %15 = getelementptr inbounds ptr, ptr %0, i64 %index
+  %16 = getelementptr inbounds ptr, ptr %0, i64 0
+  %17 = getelementptr inbounds ptr, ptr %0, i64 %induction8
+  store ptr null, ptr %15, align 16
+  store ptr %13, ptr poison, align 8
+  store ptr null, ptr %16, align 16
+  store ptr %14, ptr %17, align 8
+  %18 = getelementptr inbounds %struct, ptr %next.gep, i64 0, i32 1
+  %19 = load i32, ptr %18, align 4
+  %20 = zext i32 %19 to i64
+  %21 = getelementptr inbounds ptr, ptr %etable, i64 %20
+  %22 = load ptr, ptr %21, align 8
+  %23 = getelementptr inbounds ptr, ptr %1, i64 %index
+  %24 = getelementptr inbounds ptr, ptr %1, i64 0
+  %25 = getelementptr inbounds ptr, ptr %1, i64 %induction8
+  store ptr %22, ptr %23, align 16
+  store ptr null, ptr %24, align 16
+  store ptr null, ptr %25, align 8
+  %index.next = add nuw i64 %index, 4
+  %26 = icmp eq i64 %index.next, %n.vec
+  br i1 %26, label %middle.block, label %vector.body
+
+middle.block:                                     ; preds = %vector.body
+  %call = call ptr @bar(ptr noundef %bm, ptr noundef nonnull %0, ptr noundef nonnull %1, i32 noundef signext %mp.4.val, ptr noundef null, i32 noundef zeroext 4)
+  ret ptr %call
+}
+
+declare ptr @bar(ptr, ptr, ptr, i32, ptr, i32) local_unnamed_addr


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