[PATCH] D140680: [AArch64][MachineScheduler] Set no side effect for movprfx
Allen zhong via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 26 19:17:58 PST 2022
Allen created this revision.
Allen added reviewers: dmgreen, fhahn, paulwalker-arm.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
Allen requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
The movprfx is a vector copy, so it doesn't access memory. Set the
value of hasSideEffects 0 to avoid return true for the hasUnmodeledSideEffects(),
which will block the machine scheduler which load/store instructions.
https://reviews.llvm.org/D140680
Files:
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/test/CodeGen/AArch64/sched-movprfx.ll
Index: llvm/test/CodeGen/AArch64/sched-movprfx.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sched-movprfx.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple aarch64 -mcpu=tsv110 -mattr=+sve < %s | FileCheck %s
+
+; Check that the movprfx intrinsic does not prevent load instructions from
+; being scheduled together. As load instructions have long latency, expected
+; be preferentially issued.
+
+
+; NOTE: The unused paramter ensures z0/z1 is free, avoiding the antidependence for schedule.
+define <vscale x 2 x i64> @and_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64>* %base) {
+; CHECK-LABEL: and_i64_zero:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0]
+; CHECK-NEXT: ptrue p1.d
+; CHECK-NEXT: movprfx z0, z2
+; CHECK-NEXT: abs z0.d, p1/m, z2.d
+; CHECK-NEXT: add z0.d, z0.d, z1.d
+; CHECK-NEXT: ret
+ %data0 = tail call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %c, i1 0)
+ %data1 = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64(<vscale x 2 x i64>* %base,
+ i32 1,
+ <vscale x 2 x i1> %pg,
+ <vscale x 2 x i64> undef)
+ %out = add <vscale x 2 x i64> %data0, %data1
+ ret <vscale x 2 x i64> %out
+}
+
+declare <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64>, i1)
+declare <vscale x 2 x i64> @llvm.masked.load.nxv2i64(<vscale x 2 x i64>*, i32, <vscale x 2 x i1>, <vscale x 2 x i64>)
Index: llvm/lib/Target/AArch64/SVEInstrFormats.td
===================================================================
--- llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -7916,6 +7916,8 @@
let Inst{10} = opc{0};
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
+
+ let hasSideEffects = 0;
}
multiclass sve_int_bin_cons_misc_0_c_fexpa<string asm, SDPatternOperator op> {
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D140680.485333.patch
Type: text/x-patch
Size: 2173 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221227/018604e4/attachment.bin>
More information about the llvm-commits
mailing list