[PATCH] D140665: [SelectionDAG][RISCV][X86][AArch64][AMDGPU][PowerPC] Improve SimplifyDemandedBits for SHL with NUW/NSW flags.

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy updated this revision to Diff 485325.
liaolucy retitled this revision from "[RISCV] Add DAG combine to fold (shl nuw (aextload), C) -> (shl nuw (zextload), C)." to "[SelectionDAG][RISCV][X86][AArch64][AMDGPU][PowerPC] Improve SimplifyDemandedBits for SHL with NUW/NSW flags.".
liaolucy edited the summary of this revision.
liaolucy added a comment.
Herald added subscribers: kosarev, ecnelises, kerbowa, pengfei, shchenz, kristof.beyls, tpr, dstuttard, yaxunl, wdng, jvesely, nemanjai, kzhuravl, qcolombet.

Improve SimplifyDemandedBits for SHL with NUW/NSW flags.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140665/new/

https://reviews.llvm.org/D140665

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/arm64-shifted-sext.ll
  llvm/test/CodeGen/AArch64/load-combine.ll
  llvm/test/CodeGen/AMDGPU/shl.ll
  llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
  llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
  llvm/test/CodeGen/RISCV/aext-to-zext.ll
  llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
  llvm/test/CodeGen/X86/fp128-cast.ll
  llvm/test/CodeGen/X86/parity.ll
  llvm/test/CodeGen/X86/setcc.ll
  llvm/test/CodeGen/X86/split-store.ll
  llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll

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