[PATCH] D140674: [RISCV] Prefer ADDI over ORI if the known bits are disjoint.

[Craig Topper via Phabricator via llvm-commits]

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There is no compressed form of ORI but there is a compressed form
for ADDI.

This also works for XORI since DAGCombine will turn Xor with disjoint
bits in Or.

Note: The compressed forms require a simm6 immediate, but I'm doing
this for the full simm12 range.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140674

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/or-is-add.ll
  llvm/test/CodeGen/RISCV/rv64zba.ll
  llvm/test/CodeGen/RISCV/vararg.ll

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