[llvm] 46458aa - [NFC][AArch64] Add a few vector shuffle tests that should be `zip1`

[Roman Lebedev via llvm-commits]

Author: Roman Lebedev
Date: 2022-12-26T22:54:03+03:00
New Revision: 46458aadd427aae2254a6f219e6180252d677e45

URL: https://github.com/llvm/llvm-project/commit/46458aadd427aae2254a6f219e6180252d677e45
DIFF: https://github.com/llvm/llvm-project/commit/46458aadd427aae2254a6f219e6180252d677e45.diff

LOG: [NFC][AArch64] Add a few vector shuffle tests that should be `zip1`

At least, they are equivalent to the `@vzipNoBlend`, which is lowered into zip1.

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/aarch64-vuzp.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AArch64/aarch64-vuzp.ll b/llvm/test/CodeGen/AArch64/aarch64-vuzp.ll
index 52457f8d4cab..11f5a7c83fd1 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-vuzp.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-vuzp.ll
@@ -66,3 +66,30 @@ define <8 x i8> @vzipNoBlend(ptr %A, ptr %B) nounwind {
   %vzip = shufflevector <8 x i8> %t, <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef>, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
   ret <8 x i8> %vzip
 }
+
+; FIXME: this is identical to @vzipNoBlend
+; CHECK-LABEL: vzipNoBlendCommutted:
+; CHECK-NOT: zip1
+define <8 x i8> @vzipNoBlendCommutted(ptr %A, ptr %B) nounwind {
+  %t = load <8 x i8>, ptr %A
+  %vzip = shufflevector <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef>, <8 x i8> %t, <8 x i32> <i32 8, i32 0, i32 9, i32 1, i32 10, i32 2, i32 11, i32 3>
+  ret <8 x i8> %vzip
+}
+
+; FIXME: this is identical to @vzipNoBlend
+; CHECK-LABEL: vzipStillZExt:
+; CHECK-NOT: zip1
+define <8 x i8> @vzipStillZExt(ptr %A, ptr %B) nounwind {
+  %t = load <8 x i8>, ptr %A
+  %vzip = shufflevector <8 x i8> %t, <8 x i8> <i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <8 x i32> <i32 0, i32 9, i32 1, i32 9, i32 2, i32 9, i32 3, i32 9>
+  ret <8 x i8> %vzip
+}
+
+; FIXME: this is identical to @vzipNoBlend
+; CHECK-LABEL: vzipStillZExtCommutted:
+; CHECK-NOT: zip1
+define <8 x i8> @vzipStillZExtCommutted(ptr %A, ptr %B) nounwind {
+  %t = load <8 x i8>, ptr %A
+  %vzip = shufflevector <8 x i8> <i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <8 x i8> %t, <8 x i32> <i32 8, i32 1, i32 9, i32 1, i32 10, i32 1, i32 11, i32 1>
+  ret <8 x i8> %vzip
+}