[PATCH] D140665: [RISCV] Add DAG combine to fold (shl nuw (aextload), C) -> (shl nuw (zextload), C).

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Dec 25 22:37:40 PST 2022


craig.topper added subscribers: spatel, RKSimon, lebedev.ri.
craig.topper added a comment.

In D140665#4016600 <https://reviews.llvm.org/D140665#4016600>, @liaolucy wrote:

> In D140665#4016599 <https://reviews.llvm.org/D140665#4016599>, @craig.topper wrote:
>
>> Is this a case missing from DAGCombiner::BackwardsPropagateMask?
>
> In fact, I prefer the following modifications:
>
>   diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
>   index dbf318a85e9e..76aa3c6d7623 100644
>   --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
>   +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
>   @@ -1761,6 +1761,8 @@ bool TargetLowering::SimplifyDemandedBits(
>          }
>    
>          APInt InDemandedMask = DemandedBits.lshr(ShAmt);
>   +      if (Op.getNode()->getFlags().hasNoUnsignedWrap())
>   +        InDemandedMask.setHighBits(ShAmt);
>          if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
>                                   Depth + 1))
>            return true;
>
> But this modification, for x86 is not friendly.
>
> If there are more suggestions, please tell.

@spatel @rksimon @lebedev.ri is it a bug that we are neither demanding the upper bits for nuw/nsw nor removing the poison flags if SimplifyDemandedBits returns true?


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