[PATCH] D140665: [RISCV] Add DAG combine to fold (shl nuw (aextload), C) -> (shl nuw (zextload), C).
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 25 22:31:44 PST 2022
craig.topper added a comment.
What prevents SimplifyDemandedBits from turning this back into an aextload and causing an infinite loop.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10313
+ auto *Ld = dyn_cast<LoadSDNode>(N0);
+ if (Ld && ISD::isEXTLoad(Ld)) {
+ SDValue Res = DAG.getExtLoad(ISD::ZEXTLOAD, DL, N->getValueType(0),
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Need to check that the SHL is the only user of the load or this will duplicate a load.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10317
+ Ld->getMemoryVT(), Ld->getMemOperand());
+ return DAG.getNode(N->getOpcode(), DL, N->getValueType(0), Res,
+ N->getOperand(1));
----------------
You need to replace the chain output of the original load with the chain output of the new load.
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https://reviews.llvm.org/D140665/new/
https://reviews.llvm.org/D140665
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